Hans Petter Selasky 42fabcc35c Reduce the number of interrupts in USB host mode for the DWC OTG ... controller driver by piggybacking the SOF interrupt when issuing new and checking old transfers. Number of interrupts was reduced by 30% when doing Isochronous transfers. Use correct GINTMSK_XXX macros when accessing the DWC OTG interrupt mask register. Add code to adjust the frame interval register which influences the SOF rate. MFC after: 2 weeks		2014-05-06 09:12:32 +00:00
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at91dci_atmelarm.c
at91dci_fdt.c
at91dci.c
at91dci.h
atmegadci_atmelarm.c
atmegadci.c
atmegadci.h
avr32dci.c
avr32dci.h
dwc_otg_atmelarm.c
dwc_otg_fdt.c	Add support for specifying USB controller mode via FDT.	2014-04-18 08:31:55 +00:00
dwc_otg.c	Reduce the number of interrupts in USB host mode for the DWC OTG	2014-05-06 09:12:32 +00:00
dwc_otg.h	Improve DWC OTG USB host side support for isochronous FULL and HIGH	2014-05-05 11:50:52 +00:00
dwc_otgreg.h	Improve DWC OTG USB host side support for isochronous FULL and HIGH	2014-05-05 11:50:52 +00:00
ehci_fsl.c
ehci_imx.c	Stop calling imx51_ccm_foo() clock functions from imx6 code. Instead	2014-04-26 16:48:09 +00:00
ehci_ixp4xx.c
ehci_mv.c
ehci_pci.c
ehci.c
ehci.h
ehcireg.h
musb_otg_atmelarm.c
musb_otg.c
musb_otg.h
ohci_atmelarm.c
ohci_fdt.c
ohci_pci.c
ohci_s3c24x0.c
ohci.c
ohci.h
ohcireg.h
uhci_pci.c
uhci.c
uhci.h
uhcireg.h
usb_controller.c
uss820dci_atmelarm.c
uss820dci.c
uss820dci.h
xhci_pci.c	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00
xhci.c	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00
xhci.h	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00
xhcireg.h	Setting the IMOD value below 0x3F8 can cause IRQ lockups in the Intel	2014-04-27 15:41:44 +00:00