a806ad4021
heavy I/O load. Many thanks to LSI for continuing to support FreeBSD. PR: kern/149968 Submitted by: LSI (Tom Couch) Reported by: Kai Kockro <kkockro web de> Tested by: Kai Kockro, jpaetzel MFC after: 7 days
324 lines
9.9 KiB
C
324 lines
9.9 KiB
C
/*
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* Copyright (c) 2004-07 Applied Micro Circuits Corporation.
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* Copyright (c) 2004-05 Vinod Kashyap.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* AMCC'S 3ware driver for 9000 series storage controllers.
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*
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* Author: Vinod Kashyap
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* Modifications by: Adam Radford
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* Modifications by: Manjunath Ranganathaiah
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*/
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#ifndef TW_OSL_H
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#define TW_OSL_H
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/*
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* OS Layer internal macros, structures and functions.
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*/
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#define TW_OSLI_DEVICE_NAME "3ware 9000 series Storage Controller"
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#define TW_OSLI_MALLOC_CLASS M_TWA
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#define TW_OSLI_MAX_NUM_REQUESTS TW_CL_MAX_SIMULTANEOUS_REQUESTS
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/* Reserve two command packets. One for ioctls and one for AENs */
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#define TW_OSLI_MAX_NUM_IOS (TW_OSLI_MAX_NUM_REQUESTS - 2)
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#define TW_OSLI_MAX_NUM_AENS 0x100
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#ifdef PAE
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#define TW_OSLI_DMA_BOUNDARY (1u << 31)
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#else
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#define TW_OSLI_DMA_BOUNDARY ((bus_size_t)((uint64_t)1 << 32))
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#endif
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/* Possible values of req->state. */
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#define TW_OSLI_REQ_STATE_INIT 0x0 /* being initialized */
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#define TW_OSLI_REQ_STATE_BUSY 0x1 /* submitted to CL */
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#define TW_OSLI_REQ_STATE_PENDING 0x2 /* in pending queue */
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#define TW_OSLI_REQ_STATE_COMPLETE 0x3 /* completed by CL */
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/* Possible values of req->flags. */
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#define TW_OSLI_REQ_FLAGS_DATA_IN (1<<0) /* read request */
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#define TW_OSLI_REQ_FLAGS_DATA_OUT (1<<1) /* write request */
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#define TW_OSLI_REQ_FLAGS_DATA_COPY_NEEDED (1<<2)/* data in ccb is misaligned,
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have to copy to/from private buffer */
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#define TW_OSLI_REQ_FLAGS_MAPPED (1<<3) /* request has been mapped */
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#define TW_OSLI_REQ_FLAGS_IN_PROGRESS (1<<4) /* bus_dmamap_load returned
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EINPROGRESS */
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#define TW_OSLI_REQ_FLAGS_PASSTHRU (1<<5) /* pass through request */
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#define TW_OSLI_REQ_FLAGS_SLEEPING (1<<6) /* owner sleeping on this cmd */
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#define TW_OSLI_REQ_FLAGS_FAILED (1<<7) /* bus_dmamap_load() failed */
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#ifdef TW_OSL_DEBUG
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struct tw_osli_q_stats {
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TW_UINT32 cur_len; /* current # of items in q */
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TW_UINT32 max_len; /* max value reached by q_length */
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};
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#endif /* TW_OSL_DEBUG */
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/* Queues of OSL internal request context packets. */
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#define TW_OSLI_FREE_Q 0 /* free q */
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#define TW_OSLI_BUSY_Q 1 /* q of reqs submitted to CL */
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#define TW_OSLI_Q_COUNT 2 /* total number of queues */
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/* Driver's request packet. */
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struct tw_osli_req_context {
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struct tw_cl_req_handle req_handle;/* tag to track req b/w OSL & CL */
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struct mtx ioctl_wake_timeout_lock_handle;/* non-spin lock used to detect ioctl timeout */
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struct mtx *ioctl_wake_timeout_lock;/* ptr to above lock */
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struct twa_softc *ctlr; /* ptr to OSL's controller context */
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TW_VOID *data; /* ptr to data being passed to CL */
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TW_UINT32 length; /* length of buf being passed to CL */
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TW_UINT64 deadline;/* request timeout (in absolute time) */
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/*
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* ptr to, and length of data passed to us from above, in case a buffer
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* copy was done due to non-compliance to alignment requirements
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*/
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TW_VOID *real_data;
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TW_UINT32 real_length;
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TW_UINT32 state; /* request state */
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TW_UINT32 flags; /* request flags */
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/* error encountered before request submission to CL */
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TW_UINT32 error_code;
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/* ptr to orig req for use during callback */
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TW_VOID *orig_req;
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struct tw_cl_link link; /* to link this request in a list */
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bus_dmamap_t dma_map;/* DMA map for data */
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struct tw_cl_req_packet req_pkt;/* req pkt understood by CL */
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};
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/* Per-controller structure. */
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struct twa_softc {
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struct tw_cl_ctlr_handle ctlr_handle;
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struct tw_osli_req_context *req_ctx_buf;
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/* Controller state. */
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TW_UINT8 open;
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TW_UINT32 flags;
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TW_INT32 device_id;
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TW_UINT32 alignment;
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TW_UINT32 sg_size_factor;
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TW_VOID *non_dma_mem;
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TW_VOID *dma_mem;
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TW_UINT64 dma_mem_phys;
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/* Request queues and arrays. */
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struct tw_cl_link req_q_head[TW_OSLI_Q_COUNT];
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struct task deferred_intr_callback;/* taskqueue function */
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struct mtx io_lock_handle;/* general purpose lock */
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struct mtx *io_lock;/* ptr to general purpose lock */
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struct mtx q_lock_handle; /* queue manipulation lock */
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struct mtx *q_lock;/* ptr to queue manipulation lock */
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struct mtx sim_lock_handle;/* sim lock shared with cam */
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struct mtx *sim_lock;/* ptr to sim lock */
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struct callout watchdog_callout[2]; /* For command timout */
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TW_UINT32 watchdog_index;
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#ifdef TW_OSL_DEBUG
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struct tw_osli_q_stats q_stats[TW_OSLI_Q_COUNT];/* queue statistics */
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#endif /* TW_OSL_DEBUG */
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device_t bus_dev; /* bus device */
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struct cdev *ctrl_dev; /* control device */
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struct resource *reg_res; /* register interface window */
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TW_INT32 reg_res_id; /* register resource id */
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bus_space_handle_t bus_handle; /* bus space handle */
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bus_space_tag_t bus_tag; /* bus space tag */
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bus_dma_tag_t parent_tag; /* parent DMA tag */
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bus_dma_tag_t cmd_tag; /* DMA tag for CL's DMA'able mem */
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bus_dma_tag_t dma_tag; /* data buffer DMA tag */
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bus_dma_tag_t ioctl_tag; /* ioctl data buffer DMA tag */
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bus_dmamap_t cmd_map; /* DMA map for CL's DMA'able mem */
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bus_dmamap_t ioctl_map; /* DMA map for ioctl data buffers */
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struct resource *irq_res; /* interrupt resource */
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TW_INT32 irq_res_id; /* register resource id */
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TW_VOID *intr_handle; /* interrupt handle */
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struct sysctl_ctx_list sysctl_ctxt; /* sysctl context */
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struct sysctl_oid *sysctl_tree; /* sysctl oid */
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struct cam_sim *sim; /* sim for this controller */
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struct cam_path *path; /* peripheral, path, tgt, lun
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associated with this controller */
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};
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/*
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* Queue primitives.
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*/
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#ifdef TW_OSL_DEBUG
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#define TW_OSLI_Q_INIT(sc, q_type) do { \
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(sc)->q_stats[q_type].cur_len = 0; \
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(sc)->q_stats[q_type].max_len = 0; \
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} while(0)
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#define TW_OSLI_Q_INSERT(sc, q_type) do { \
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struct tw_osli_q_stats *q_stats = &((sc)->q_stats[q_type]); \
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\
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if (++(q_stats->cur_len) > q_stats->max_len) \
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q_stats->max_len = q_stats->cur_len; \
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} while(0)
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#define TW_OSLI_Q_REMOVE(sc, q_type) \
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(sc)->q_stats[q_type].cur_len--
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#else /* TW_OSL_DEBUG */
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#define TW_OSLI_Q_INIT(sc, q_index)
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#define TW_OSLI_Q_INSERT(sc, q_index)
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#define TW_OSLI_Q_REMOVE(sc, q_index)
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#endif /* TW_OSL_DEBUG */
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/* Initialize a queue of requests. */
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static __inline TW_VOID
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tw_osli_req_q_init(struct twa_softc *sc, TW_UINT8 q_type)
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{
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TW_CL_Q_INIT(&(sc->req_q_head[q_type]));
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TW_OSLI_Q_INIT(sc, q_type);
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}
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/* Insert the given request at the head of the given queue (q_type). */
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static __inline TW_VOID
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tw_osli_req_q_insert_head(struct tw_osli_req_context *req, TW_UINT8 q_type)
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{
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mtx_lock_spin(req->ctlr->q_lock);
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TW_CL_Q_INSERT_HEAD(&(req->ctlr->req_q_head[q_type]), &(req->link));
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TW_OSLI_Q_INSERT(req->ctlr, q_type);
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mtx_unlock_spin(req->ctlr->q_lock);
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}
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/* Insert the given request at the tail of the given queue (q_type). */
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static __inline TW_VOID
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tw_osli_req_q_insert_tail(struct tw_osli_req_context *req, TW_UINT8 q_type)
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{
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mtx_lock_spin(req->ctlr->q_lock);
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TW_CL_Q_INSERT_TAIL(&(req->ctlr->req_q_head[q_type]), &(req->link));
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TW_OSLI_Q_INSERT(req->ctlr, q_type);
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mtx_unlock_spin(req->ctlr->q_lock);
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}
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/* Remove and return the request at the head of the given queue (q_type). */
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static __inline struct tw_osli_req_context *
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tw_osli_req_q_remove_head(struct twa_softc *sc, TW_UINT8 q_type)
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{
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struct tw_osli_req_context *req = NULL;
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struct tw_cl_link *link;
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mtx_lock_spin(sc->q_lock);
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if ((link = TW_CL_Q_FIRST_ITEM(&(sc->req_q_head[q_type]))) !=
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TW_CL_NULL) {
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req = TW_CL_STRUCT_HEAD(link,
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struct tw_osli_req_context, link);
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TW_CL_Q_REMOVE_ITEM(&(sc->req_q_head[q_type]), &(req->link));
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TW_OSLI_Q_REMOVE(sc, q_type);
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}
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mtx_unlock_spin(sc->q_lock);
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return(req);
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}
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/* Remove the given request from the given queue (q_type). */
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static __inline TW_VOID
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tw_osli_req_q_remove_item(struct tw_osli_req_context *req, TW_UINT8 q_type)
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{
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mtx_lock_spin(req->ctlr->q_lock);
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TW_CL_Q_REMOVE_ITEM(&(req->ctlr->req_q_head[q_type]), &(req->link));
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TW_OSLI_Q_REMOVE(req->ctlr, q_type);
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mtx_unlock_spin(req->ctlr->q_lock);
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}
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#ifdef TW_OSL_DEBUG
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extern TW_INT32 TW_DEBUG_LEVEL_FOR_OSL;
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#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...) \
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if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
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device_printf(sc->bus_dev, "%s: " fmt "\n", \
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__func__, ##args)
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#define tw_osli_dbg_printf(dbg_level, fmt, args...) \
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if (dbg_level <= TW_DEBUG_LEVEL_FOR_OSL) \
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printf("%s: " fmt "\n", __func__, ##args)
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#else /* TW_OSL_DEBUG */
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#define tw_osli_dbg_dprintf(dbg_level, sc, fmt, args...)
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#define tw_osli_dbg_printf(dbg_level, fmt, args...)
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#endif /* TW_OSL_DEBUG */
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/* For regular printing. */
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#define twa_printf(sc, fmt, args...) \
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device_printf(((struct twa_softc *)(sc))->bus_dev, fmt, ##args)
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/* For printing in the "consistent error reporting" format. */
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#define tw_osli_printf(sc, err_specific_desc, args...) \
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device_printf((sc)->bus_dev, \
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"%s: (0x%02X: 0x%04X): %s: " err_specific_desc "\n", ##args)
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#endif /* TW_OSL_H */
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