100 lines
3.8 KiB
C
100 lines
3.8 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_EEPROM_V1_H_
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#define _ATH_AH_EEPROM_V1_H_
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#include "ah_eeprom.h"
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/*
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* EEPROM defines for Version 1 Crete EEPROM.
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*
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* The EEPROM is segmented into three sections:
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*
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* PCI/Cardbus default configuration settings
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* Cardbus CIS tuples and vendor-specific data
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* Atheros-specific data
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*
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* EEPROM entries are read 32-bits at a time through the PCI bus
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* interface but are all 16-bit values.
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*
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* Access to the Atheros-specific data is controlled by protection
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* bits and the data is checksum'd. The driver reads the Atheros
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* data from the EEPROM at attach and caches it in its private state.
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* This data includes the local regulatory domain, channel calibration
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* settings, and phy-related configuration settings.
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*/
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#define AR_EEPROM_MAC(i) (0x1f-(i))/* MAC address word */
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#define AR_EEPROM_MAGIC 0x3d /* magic number */
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#define AR_EEPROM_PROTECT 0x3f /* Atheros segment protect register */
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#define AR_EEPROM_PROTOTECT_WP_128_191 0x80
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#define AR_EEPROM_REG_DOMAIN 0xbf /* Current regulatory domain register */
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#define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */
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#define AR_EEPROM_ATHEROS_MAX 64 /* 64x2=128 bytes of EEPROM settings */
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#define AR_EEPROM_ATHEROS(n) (AR_EEPROM_ATHEROS_BASE+(n))
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#define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1)
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#define AR_EEPROM_ATHEROS_TP_SETTINGS 0x09 /* Transmit power settings */
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#define AR_REG_DOMAINS_MAX 4 /* # of Regulatory Domains */
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#define AR_CHANNELS_MAX 5 /* # of Channel calibration groups */
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#define AR_TP_SETTINGS_SIZE 11 /* # locations/Channel group */
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#define AR_TP_SCALING_ENTRIES 11 /* # entries in transmit power dBm->pcdac */
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/*
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* NB: we store the rfsilent select+polarity data packed
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* with the encoding used in later parts so values
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* returned to applications are consistent.
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*/
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#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
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#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
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#define AR_EEPROM_RFSILENT_POLARITY 0x0002
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#define AR_EEPROM_RFSILENT_POLARITY_S 1
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#define AR_I2DBM(x) ((uint8_t)((x * 2) + 3))
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/*
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* Transmit power and channel calibration settings.
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*/
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struct tpcMap {
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uint8_t pcdac[AR_TP_SCALING_ENTRIES];
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uint8_t gainF[AR_TP_SCALING_ENTRIES];
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uint8_t rate36;
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uint8_t rate48;
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uint8_t rate54;
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uint8_t regdmn[AR_REG_DOMAINS_MAX];
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};
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/*
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* Information retrieved from EEPROM.
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*/
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typedef struct {
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uint16_t ee_version; /* Version field */
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uint16_t ee_protect; /* EEPROM protect field */
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uint16_t ee_antenna; /* Antenna Settings */
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uint16_t ee_biasCurrents; /* OB, DB */
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uint8_t ee_thresh62; /* thresh62 */
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uint8_t ee_xlnaOn; /* External LNA timing */
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uint8_t ee_xpaOff; /* Extern output stage timing */
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uint8_t ee_xpaOn; /* Extern output stage timing */
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uint8_t ee_rfKill; /* Single low bit signalling if RF Kill is implemented */
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uint8_t ee_devType; /* Type: PCI, miniPCI, CB */
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uint8_t ee_regDomain[AR_REG_DOMAINS_MAX];
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/* calibrated reg domains */
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struct tpcMap ee_tpc[AR_CHANNELS_MAX];
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} HAL_EEPROM_v1;
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#endif /* _ATH_AH_EEPROM_V1_H_ */
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