407 lines
13 KiB
C
407 lines
13 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This header file defines the registers of the Mentor Graphics USB OnTheGo
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* Inventra chip.
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*/
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#ifndef _MUSB2_OTG_H_
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#define _MUSB2_OTG_H_
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#define MUSB2_MAX_DEVICES (USB_MIN_DEVICES + 1)
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/* Common registers */
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#define MUSB2_REG_FADDR 0x0000 /* function address register */
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#define MUSB2_MASK_FADDR 0x7F
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#define MUSB2_REG_POWER 0x0001 /* power register */
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#define MUSB2_MASK_SUSPM_ENA 0x01
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#define MUSB2_MASK_SUSPMODE 0x02
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#define MUSB2_MASK_RESUME 0x04
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#define MUSB2_MASK_RESET 0x08
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#define MUSB2_MASK_HSMODE 0x10
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#define MUSB2_MASK_HSENAB 0x20
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#define MUSB2_MASK_SOFTC 0x40
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#define MUSB2_MASK_ISOUPD 0x80
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/* Endpoint interrupt handling */
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#define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */
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#define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */
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#define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */
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#define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */
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#define MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */
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/* Common interrupt handling */
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#define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */
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#define MUSB2_MASK_ISUSP 0x01
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#define MUSB2_MASK_IRESUME 0x02
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#define MUSB2_MASK_IRESET 0x04
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#define MUSB2_MASK_IBABBLE 0x04
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#define MUSB2_MASK_ISOF 0x08
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#define MUSB2_MASK_ICONN 0x10
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#define MUSB2_MASK_IDISC 0x20
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#define MUSB2_MASK_ISESSRQ 0x40
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#define MUSB2_MASK_IVBUSERR 0x80
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#define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */
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#define MUSB2_REG_FRAME 0x000C /* USB frame register */
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#define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */
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#define MUSB2_REG_EPINDEX 0x000E /* endpoint index register */
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#define MUSB2_MASK_EPINDEX 0x0F
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#define MUSB2_REG_TESTMODE 0x000F /* test mode register */
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#define MUSB2_MASK_TSE0_NAK 0x01
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#define MUSB2_MASK_TJ 0x02
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#define MUSB2_MASK_TK 0x04
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#define MUSB2_MASK_TPACKET 0x08
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#define MUSB2_MASK_TFORCE_HS 0x10
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#define MUSB2_MASK_TFORCE_LS 0x20
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#define MUSB2_MASK_TFIFO_ACC 0x40
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#define MUSB2_MASK_TFORCE_HC 0x80
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#define MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */
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#define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */
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#define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */
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#define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_CSRL_TXPKTRDY 0x01
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#define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02
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#define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */
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#define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */
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#define MUSB2_MASK_CSRL_TXFFLUSH 0x08
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#define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */
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#define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */
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#define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */
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#define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */
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#define MUSB2_MASK_CSRL_TXDT_CLR 0x40
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#define MUSB2_MASK_CSRL_TXINCOMP 0x80
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/* Device Side Mode */
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#define MUSB2_MASK_CSR0L_RXPKTRDY 0x01
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#define MUSB2_MASK_CSR0L_TXPKTRDY 0x02
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#define MUSB2_MASK_CSR0L_SENTSTALL 0x04
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#define MUSB2_MASK_CSR0L_DATAEND 0x08
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#define MUSB2_MASK_CSR0L_SETUPEND 0x10
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#define MUSB2_MASK_CSR0L_SENDSTALL 0x20
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#define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40
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#define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80
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/* Host Side Mode */
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#define MUSB2_MASK_CSR0L_RXSTALL 0x04
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#define MUSB2_MASK_CSR0L_SETUPPKT 0x08
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#define MUSB2_MASK_CSR0L_ERROR 0x10
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#define MUSB2_MASK_CSR0L_REQPKT 0x20
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#define MUSB2_MASK_CSR0L_STATUSPKT 0x40
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#define MUSB2_MASK_CSR0L_NAKTIMO 0x80
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#define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */
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#define MUSB2_MASK_CSRH_TXDT_WR 0x02 /* Host Mode */
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#define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04
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#define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08
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#define MUSB2_MASK_CSRH_TXDMAREQENA 0x10
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#define MUSB2_MASK_CSRH_RXMODE 0x00
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#define MUSB2_MASK_CSRH_TXMODE 0x20
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#define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */
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#define MUSB2_MASK_CSRH_TXAUTOSET 0x80
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#define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */
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#define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */
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#define MUSB2_MASK_CSR0H_DT_SET 0x04 /* Host Side */
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#define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */
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#define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_CSRL_RXPKTRDY 0x01
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#define MUSB2_MASK_CSRL_RXFIFOFULL 0x02
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#define MUSB2_MASK_CSRL_RXOVERRUN 0x04
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#define MUSB2_MASK_CSRL_RXDATAERR 0x08
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#define MUSB2_MASK_CSRL_RXFFLUSH 0x10
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#define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */
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#define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */
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#define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */
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#define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */
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#define MUSB2_MASK_CSRL_RXDT_CLR 0x80
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#define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_CSRH_RXINCOMP 0x01
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#define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */
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#define MUSB2_MASK_CSRH_RXDT_SET 0x04 /* Host Mode */
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#define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08
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#define MUSB2_MASK_CSRH_RXNYET 0x10
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#define MUSB2_MASK_CSRH_RXDMAREQENA 0x20
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#define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */
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#define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */
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#define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80
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#define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_RXCOUNT 0xFFFF
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#define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR)
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/* Host Mode */
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#define MUSB2_MASK_TI_SPEED 0xC0
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#define MUSB2_MASK_TI_SPEED_LO 0xC0
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#define MUSB2_MASK_TI_SPEED_FS 0x80
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#define MUSB2_MASK_TI_SPEED_HS 0x40
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#define MUSB2_MASK_TI_PROTO_CTRL 0x00
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#define MUSB2_MASK_TI_PROTO_ISOC 0x10
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#define MUSB2_MASK_TI_PROTO_BULK 0x20
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#define MUSB2_MASK_TI_PROTO_INTR 0x30
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#define MUSB2_MASK_TI_EP_NUM 0x0F
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#define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_NAKLIMIT 0xFF
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#define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR)
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#define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */
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#define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */
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#define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n)))
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#define MUSB2_REG_CONFDATA 0x000F /* EPN=0 */
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#define MUSB2_MASK_CD_UTMI_DW 0x01
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#define MUSB2_MASK_CD_SOFTCONE 0x02
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#define MUSB2_MASK_CD_DYNFIFOSZ 0x04
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#define MUSB2_MASK_CD_HBTXE 0x08
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#define MUSB2_MASK_CD_HBRXE 0x10
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#define MUSB2_MASK_CD_BIGEND 0x20
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#define MUSB2_MASK_CD_MPTXE 0x40
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#define MUSB2_MASK_CD_MPRXE 0x80
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/* Various registers */
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#define MUSB2_REG_DEVCTL 0x0060
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#define MUSB2_MASK_SESS 0x01
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#define MUSB2_MASK_HOSTREQ 0x02
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#define MUSB2_MASK_HOSTMD 0x04
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#define MUSB2_MASK_VBUS0 0x08
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#define MUSB2_MASK_VBUS1 0x10
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#define MUSB2_MASK_LSDEV 0x20
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#define MUSB2_MASK_FSDEV 0x40
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#define MUSB2_MASK_BDEV 0x80
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#define MUSB2_REG_MISC 0x0061
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#define MUSB2_MASK_RXEDMA 0x01
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#define MUSB2_MASK_TXEDMA 0x02
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#define MUSB2_REG_TXFIFOSZ 0x0062
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#define MUSB2_REG_RXFIFOSZ 0x0063
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#define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */
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#define MUSB2_MASK_FIFOSZ 0x0F
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#define MUSB2_VAL_FIFOSZ_8 0
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#define MUSB2_VAL_FIFOSZ_16 1
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#define MUSB2_VAL_FIFOSZ_32 2
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#define MUSB2_VAL_FIFOSZ_64 3
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#define MUSB2_VAL_FIFOSZ_128 4
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#define MUSB2_VAL_FIFOSZ_256 5
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#define MUSB2_VAL_FIFOSZ_512 6
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#define MUSB2_VAL_FIFOSZ_1024 7
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#define MUSB2_VAL_FIFOSZ_2048 8
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#define MUSB2_VAL_FIFOSZ_4096 9
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#define MUSB2_REG_TXFIFOADD 0x0064
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#define MUSB2_REG_RXFIFOADD 0x0066
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#define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */
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#define MUSB2_REG_VSTATUS 0x0068
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#define MUSB2_REG_VCONTROL 0x0068
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#define MUSB2_REG_HWVERS 0x006C
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#define MUSB2_REG_ULPI_BASE 0x0070
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#define MUSB2_REG_EPINFO 0x0078
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#define MUSB2_MASK_NRXEP 0xF0
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#define MUSB2_MASK_NTXEP 0x0F
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#define MUSB2_REG_RAMINFO 0x0079
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#define MUSB2_REG_LINKINFO 0x007A
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#define MUSB2_REG_VPLEN 0x007B
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#define MUSB2_MASK_VPLEN 0xFF
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#define MUSB2_REG_HS_EOF1 0x007C
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#define MUSB2_REG_FS_EOF1 0x007D
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#define MUSB2_REG_LS_EOF1 0x007E
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#define MUSB2_REG_SOFT_RST 0x007F
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#define MUSB2_MASK_SRST 0x01
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#define MUSB2_MASK_SRSTX 0x02
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#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n))
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#define MUSB2_REG_RXDBDIS 0x0340
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#define MUSB2_REG_TXDBDIS 0x0342
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#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */
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#define MUSB2_REG_CHIRPTO 0x0344
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#define MUSB2_REG_HSRESUM 0x0346
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/* Host Mode only registers */
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#define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n)))
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#define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n)))
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#define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n)))
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#define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n)))
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#define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n)))
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#define MUSB2_REG_RXHPORT(n) (0x0087 + (8*(n)))
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#define MUSB2_EP_MAX 16 /* maximum number of endpoints */
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#define MUSB2_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define MUSB2_WRITE_2(sc, reg, data) \
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bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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#define MUSB2_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define MUSB2_WRITE_1(sc, reg, data) \
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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struct musbotg_td;
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struct musbotg_softc;
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typedef uint8_t (musbotg_cmd_t)(struct musbotg_td *td);
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struct musbotg_dma {
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struct musbotg_softc *sc;
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uint32_t dma_chan;
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uint8_t busy:1;
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uint8_t complete:1;
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uint8_t error:1;
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};
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struct musbotg_td {
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struct musbotg_td *obj_next;
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musbotg_cmd_t *func;
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struct usb_page_cache *pc;
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uint32_t offset;
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uint32_t remainder;
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uint16_t max_frame_size; /* packet_size * mult */
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uint8_t ep_no;
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uint8_t error:1;
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uint8_t alt_next:1;
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uint8_t short_pkt:1;
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uint8_t support_multi_buffer:1;
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uint8_t did_stall:1;
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uint8_t dma_enabled:1;
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};
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struct musbotg_std_temp {
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musbotg_cmd_t *func;
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struct usb_page_cache *pc;
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struct musbotg_td *td;
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struct musbotg_td *td_next;
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uint32_t len;
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uint32_t offset;
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uint16_t max_frame_size;
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uint8_t short_pkt;
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/*
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* short_pkt = 0: transfer should be short terminated
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* short_pkt = 1: transfer should not be short terminated
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*/
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uint8_t setup_alt_next;
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uint8_t did_stall;
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};
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struct musbotg_config_desc {
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struct usb_config_descriptor confd;
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struct usb_interface_descriptor ifcd;
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struct usb_endpoint_descriptor endpd;
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} __packed;
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union musbotg_hub_temp {
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uWord wValue;
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struct usb_port_status ps;
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};
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struct musbotg_flags {
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uint8_t change_connect:1;
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uint8_t change_suspend:1;
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uint8_t status_suspend:1; /* set if suspended */
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uint8_t status_vbus:1; /* set if present */
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uint8_t status_bus_reset:1; /* set if reset complete */
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uint8_t status_high_speed:1; /* set if High Speed is selected */
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uint8_t remote_wakeup:1;
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uint8_t self_powered:1;
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uint8_t clocks_off:1;
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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};
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struct musbotg_softc {
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struct usb_bus sc_bus;
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union musbotg_hub_temp sc_hub_temp;
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struct usb_hw_ep_profile sc_hw_ep_profile[16];
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struct usb_device *sc_devices[MUSB2_MAX_DEVICES];
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struct resource *sc_io_res;
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struct resource *sc_irq_res;
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void *sc_intr_hdl;
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bus_size_t sc_io_size;
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bus_space_tag_t sc_io_tag;
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bus_space_handle_t sc_io_hdl;
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void (*sc_clocks_on) (void *arg);
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void (*sc_clocks_off) (void *arg);
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void *sc_clocks_arg;
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uint32_t sc_bounce_buf[(1024 * 3) / 4]; /* bounce buffer */
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uint8_t sc_ep_max; /* maximum number of RX and TX
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* endpoints supported */
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root HUB config */
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uint8_t sc_ep0_busy; /* set if ep0 is busy */
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uint8_t sc_ep0_cmd; /* pending commands */
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uint8_t sc_conf_data; /* copy of hardware register */
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uint8_t sc_hub_idata[1];
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struct musbotg_flags sc_flags;
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};
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/* prototypes */
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usb_error_t musbotg_init(struct musbotg_softc *sc);
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void musbotg_uninit(struct musbotg_softc *sc);
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void musbotg_suspend(struct musbotg_softc *sc);
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void musbotg_resume(struct musbotg_softc *sc);
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void musbotg_interrupt(struct musbotg_softc *sc);
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void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on);
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#endif /* _MUSB2_OTG_H_ */
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