112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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/* Adc DC Offset Cal aliases */
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#define totalAdcDcOffsetIOddPhase(i) caldata[0][i].s
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#define totalAdcDcOffsetIEvenPhase(i) caldata[1][i].s
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#define totalAdcDcOffsetQOddPhase(i) caldata[2][i].s
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#define totalAdcDcOffsetQEvenPhase(i) caldata[3][i].s
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void
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ar5416AdcDcCalCollect(struct ath_hal *ah)
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{
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struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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cal->totalAdcDcOffsetIOddPhase(i) += (int32_t)
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OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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cal->totalAdcDcOffsetIEvenPhase(i) += (int32_t)
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OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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cal->totalAdcDcOffsetQOddPhase(i) += (int32_t)
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OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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cal->totalAdcDcOffsetQEvenPhase(i) += (int32_t)
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OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
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cal->calSamples, i,
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cal->totalAdcDcOffsetIOddPhase(i),
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cal->totalAdcDcOffsetIEvenPhase(i),
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cal->totalAdcDcOffsetQOddPhase(i),
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cal->totalAdcDcOffsetQEvenPhase(i));
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}
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}
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void
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ar5416AdcDcCalibration(struct ath_hal *ah, uint8_t numChains)
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{
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struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
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const HAL_PERCAL_DATA *calData = cal->cal_curr->calData;
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uint32_t numSamples;
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int i;
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numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
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for (i = 0; i < numChains; i++) {
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uint32_t iOddMeasOffset = cal->totalAdcDcOffsetIOddPhase(i);
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uint32_t iEvenMeasOffset = cal->totalAdcDcOffsetIEvenPhase(i);
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int32_t qOddMeasOffset = cal->totalAdcDcOffsetQOddPhase(i);
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int32_t qEvenMeasOffset = cal->totalAdcDcOffsetQEvenPhase(i);
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int32_t qDcMismatch, iDcMismatch;
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uint32_t val;
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"Starting ADC DC Offset Cal for Chain %d\n", i);
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HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_i = %d\n",
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iOddMeasOffset);
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HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_i = %d\n",
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iEvenMeasOffset);
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HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_odd_q = %d\n",
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qOddMeasOffset);
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HALDEBUG(ah, HAL_DEBUG_PERCAL, " pwr_meas_even_q = %d\n",
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qEvenMeasOffset);
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HALASSERT(numSamples);
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iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
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numSamples) & 0x1ff;
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qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
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numSamples) & 0x1ff;
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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" dc_offset_mismatch_i = 0x%08x\n", iDcMismatch);
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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" dc_offset_mismatch_q = 0x%08x\n", qDcMismatch);
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val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
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val &= 0xc0000fff;
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val |= (qDcMismatch << 12) | (iDcMismatch << 21);
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OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"ADC DC Offset Cal done for Chain %d\n", i);
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}
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OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
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AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
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}
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