155d93ad41
the completion schedule from the hardware and returns AH_TRUE if the hardware supports multi-rate retries (AR5212 and above); and returns AH_FALSE if the hardware doesn't support multi-rate retries. The sample rate module directly reads the TX completion descriptor and extracts the TX schedule information from that. It will be updated in a future commit to instead use this method to determine the completion schedule.
673 lines
18 KiB
C
673 lines
18 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2006 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_desc.h"
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#include "ar5211/ar5211.h"
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#include "ar5211/ar5211reg.h"
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#include "ar5211/ar5211desc.h"
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/*
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* Update Tx FIFO trigger level.
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*
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* Set bIncTrigLevel to TRUE to increase the trigger level.
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* Set bIncTrigLevel to FALSE to decrease the trigger level.
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*
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* Returns TRUE if the trigger level was updated
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*/
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HAL_BOOL
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ar5211UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
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{
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uint32_t curTrigLevel, txcfg;
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HAL_INT ints = ar5211GetInterrupts(ah);
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/*
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* Disable chip interrupts. This is because halUpdateTxTrigLevel
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* is called from both ISR and non-ISR contexts.
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*/
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ar5211SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
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txcfg = OS_REG_READ(ah, AR_TXCFG);
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curTrigLevel = (txcfg & AR_TXCFG_FTRIG_M) >> AR_TXCFG_FTRIG_S;
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if (bIncTrigLevel){
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/* increase the trigger level */
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curTrigLevel = curTrigLevel +
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((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
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} else {
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/* decrease the trigger level if not already at the minimum */
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if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
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/* decrease the trigger level */
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curTrigLevel--;
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} else {
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/* no update to the trigger level */
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/* re-enable chip interrupts */
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ar5211SetInterrupts(ah, ints);
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return AH_FALSE;
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}
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}
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/* Update the trigger level */
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OS_REG_WRITE(ah, AR_TXCFG, (txcfg &~ AR_TXCFG_FTRIG_M) |
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((curTrigLevel << AR_TXCFG_FTRIG_S) & AR_TXCFG_FTRIG_M));
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/* re-enable chip interrupts */
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ar5211SetInterrupts(ah, ints);
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return AH_TRUE;
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}
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/*
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* Set the properties of the tx queue with the parameters
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* from qInfo. The queue must previously have been setup
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* with a call to ar5211SetupTxQueue.
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*/
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HAL_BOOL
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ar5211SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
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}
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/*
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* Return the properties for the specified tx queue.
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*/
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HAL_BOOL
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ar5211GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
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}
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/*
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* Allocate and initialize a tx DCU/QCU combination.
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*/
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int
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ar5211SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
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const HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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HAL_TX_QUEUE_INFO *qi;
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int q;
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switch (type) {
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case HAL_TX_QUEUE_BEACON:
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q = 9;
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break;
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case HAL_TX_QUEUE_CAB:
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q = 8;
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break;
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case HAL_TX_QUEUE_DATA:
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q = 0;
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if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)
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return q;
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",
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__func__, type);
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return -1;
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}
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
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__func__, q);
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return -1;
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}
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OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
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qi->tqi_type = type;
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if (qInfo == AH_NULL) {
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/* by default enable OK+ERR+DESC+URN interrupts */
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qi->tqi_qflags =
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HAL_TXQ_TXOKINT_ENABLE
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| HAL_TXQ_TXERRINT_ENABLE
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| HAL_TXQ_TXDESCINT_ENABLE
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| HAL_TXQ_TXURNINT_ENABLE
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;
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qi->tqi_aifs = INIT_AIFS;
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qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
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qi->tqi_cwmax = INIT_CWMAX;
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qi->tqi_shretry = INIT_SH_RETRY;
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qi->tqi_lgretry = INIT_LG_RETRY;
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} else
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(void) ar5211SetTxQueueProps(ah, q, qInfo);
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return q;
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}
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/*
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* Update the h/w interrupt registers to reflect a tx q's configuration.
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*/
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static void
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setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
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"%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__
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, ahp->ah_txOkInterruptMask
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, ahp->ah_txErrInterruptMask
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, ahp->ah_txDescInterruptMask
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, ahp->ah_txEolInterruptMask
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, ahp->ah_txUrnInterruptMask
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);
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OS_REG_WRITE(ah, AR_IMR_S0,
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SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
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| SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
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);
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OS_REG_WRITE(ah, AR_IMR_S1,
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SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
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| SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
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);
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OS_REG_RMW_FIELD(ah, AR_IMR_S2,
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AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
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}
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/*
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* Free a tx DCU/QCU combination.
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*/
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HAL_BOOL
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ar5211ReleaseTxQueue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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HAL_TX_QUEUE_INFO *qi;
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
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__func__, q);
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return AH_FALSE;
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}
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
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qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
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ahp->ah_txOkInterruptMask &= ~(1 << q);
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ahp->ah_txErrInterruptMask &= ~(1 << q);
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ahp->ah_txDescInterruptMask &= ~(1 << q);
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ahp->ah_txEolInterruptMask &= ~(1 << q);
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ahp->ah_txUrnInterruptMask &= ~(1 << q);
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setTxQInterrupts(ah, qi);
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return AH_TRUE;
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}
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/*
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* Set the retry, aifs, cwmin/max, readyTime regs for specified queue
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*/
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HAL_BOOL
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ar5211ResetTxQueue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5211 *ahp = AH5211(ah);
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const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
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HAL_TX_QUEUE_INFO *qi;
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uint32_t cwMin, chanCwMin, value;
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
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__func__, q);
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return AH_TRUE; /* XXX??? */
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}
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if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
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/*
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* Select cwmin according to channel type.
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* NB: chan can be NULL during attach
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*/
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if (chan && IEEE80211_IS_CHAN_B(chan))
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chanCwMin = INIT_CWMIN_11B;
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else
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chanCwMin = INIT_CWMIN;
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/* make sure that the CWmin is of the form (2^n - 1) */
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for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
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;
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} else
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cwMin = qi->tqi_cwmin;
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/* set cwMin/Max and AIFS values */
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OS_REG_WRITE(ah, AR_DLCL_IFS(q),
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SM(cwMin, AR_D_LCL_IFS_CWMIN)
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| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
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| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
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/* Set retry limit values */
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OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
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SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
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| SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
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| SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
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| SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
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);
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/* enable early termination on the QCU */
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OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
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if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
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/* Configure DCU to use the global sequence count */
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OS_REG_WRITE(ah, AR_DMISC(q), AR5311_D_MISC_SEQ_NUM_CONTROL);
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}
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/* multiqueue support */
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if (qi->tqi_cbrPeriod) {
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OS_REG_WRITE(ah, AR_QCBRCFG(q),
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SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
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| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
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OS_REG_WRITE(ah, AR_QMISC(q),
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OS_REG_READ(ah, AR_QMISC(q)) |
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AR_Q_MISC_FSP_CBR |
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(qi->tqi_cbrOverflowLimit ?
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AR_Q_MISC_CBR_EXP_CNTR_LIMIT : 0));
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}
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if (qi->tqi_readyTime) {
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OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
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SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
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AR_Q_RDYTIMECFG_EN);
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}
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if (qi->tqi_burstTime) {
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OS_REG_WRITE(ah, AR_DCHNTIME(q),
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SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
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AR_D_CHNTIME_EN);
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if (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE) {
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OS_REG_WRITE(ah, AR_QMISC(q),
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OS_REG_READ(ah, AR_QMISC(q)) |
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AR_Q_MISC_RDYTIME_EXP_POLICY);
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}
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}
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if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) {
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OS_REG_WRITE(ah, AR_DMISC(q),
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OS_REG_READ(ah, AR_DMISC(q)) |
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AR_D_MISC_POST_FR_BKOFF_DIS);
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}
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if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) {
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OS_REG_WRITE(ah, AR_DMISC(q),
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OS_REG_READ(ah, AR_DMISC(q)) |
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AR_D_MISC_FRAG_BKOFF_EN);
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}
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_BEACON:
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/* Configure QCU for beacons */
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OS_REG_WRITE(ah, AR_QMISC(q),
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OS_REG_READ(ah, AR_QMISC(q))
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| AR_Q_MISC_FSP_DBA_GATED
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| AR_Q_MISC_BEACON_USE
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| AR_Q_MISC_CBR_INCR_DIS1);
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/* Configure DCU for beacons */
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value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
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| AR_D_MISC_BEACON_USE | AR_D_MISC_POST_FR_BKOFF_DIS;
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if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
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value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
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OS_REG_WRITE(ah, AR_DMISC(q), value);
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break;
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case HAL_TX_QUEUE_CAB:
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/* Configure QCU for CAB (Crap After Beacon) frames */
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OS_REG_WRITE(ah, AR_QMISC(q),
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OS_REG_READ(ah, AR_QMISC(q))
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| AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1
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| AR_Q_MISC_CBR_INCR_DIS0 | AR_Q_MISC_RDYTIME_EXP_POLICY);
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value = (ahp->ah_beaconInterval
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- (ath_hal_sw_beacon_response_time - ath_hal_dma_beacon_response_time)
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- ath_hal_additional_swba_backoff) * 1024;
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OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN);
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/* Configure DCU for CAB */
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value = (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S);
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if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU)
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value |= AR5311_D_MISC_SEQ_NUM_CONTROL;
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OS_REG_WRITE(ah, AR_QMISC(q), value);
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break;
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default:
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/* NB: silence compiler */
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break;
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}
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/*
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* Always update the secondary interrupt mask registers - this
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* could be a new queue getting enabled in a running system or
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* hw getting re-initialized during a reset!
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*
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* Since we don't differentiate between tx interrupts corresponding
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* to individual queues - secondary tx mask regs are always unmasked;
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* tx interrupts are enabled/disabled for all queues collectively
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* using the primary mask reg
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*/
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if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
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ahp->ah_txOkInterruptMask |= 1 << q;
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else
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ahp->ah_txOkInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
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ahp->ah_txErrInterruptMask |= 1 << q;
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else
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ahp->ah_txErrInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
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ahp->ah_txDescInterruptMask |= 1 << q;
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else
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ahp->ah_txDescInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
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ahp->ah_txEolInterruptMask |= 1 << q;
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else
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ahp->ah_txEolInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
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ahp->ah_txUrnInterruptMask |= 1 << q;
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else
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ahp->ah_txUrnInterruptMask &= ~(1 << q);
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setTxQInterrupts(ah, qi);
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return AH_TRUE;
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}
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/*
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* Get the TXDP for the specified data queue.
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*/
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uint32_t
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ar5211GetTxDP(struct ath_hal *ah, u_int q)
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{
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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return OS_REG_READ(ah, AR_QTXDP(q));
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}
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/*
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* Set the TxDP for the specified tx queue.
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*/
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HAL_BOOL
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ar5211SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
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{
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
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/*
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* Make sure that TXE is deasserted before setting the TXDP. If TXE
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* is still asserted, setting TXDP will have no effect.
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*/
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HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
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OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
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return AH_TRUE;
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}
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/*
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* Set Transmit Enable bits for the specified queues.
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*/
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HAL_BOOL
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ar5211StartTxDma(struct ath_hal *ah, u_int q)
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|
{
|
|
HALASSERT(q < HAL_NUM_TX_QUEUES);
|
|
HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
|
|
/* Check that queue is not already active */
|
|
HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1<<q)) == 0);
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
|
|
|
|
/* Check to be sure we're not enabling a q that has its TXD bit set. */
|
|
HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Return the number of frames pending on the specified queue.
|
|
*/
|
|
uint32_t
|
|
ar5211NumTxPending(struct ath_hal *ah, u_int q)
|
|
{
|
|
uint32_t n;
|
|
|
|
HALASSERT(q < HAL_NUM_TX_QUEUES);
|
|
HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
|
|
n = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT_M;
|
|
/*
|
|
* Pending frame count (PFC) can momentarily go to zero
|
|
* while TXE remains asserted. In other words a PFC of
|
|
* zero is not sufficient to say that the queue has stopped.
|
|
*/
|
|
if (n == 0 && (OS_REG_READ(ah, AR_Q_TXE) & (1<<q)))
|
|
n = 1; /* arbitrarily pick 1 */
|
|
return n;
|
|
}
|
|
|
|
/*
|
|
* Stop transmit on the specified queue
|
|
*/
|
|
HAL_BOOL
|
|
ar5211StopTxDma(struct ath_hal *ah, u_int q)
|
|
{
|
|
int i;
|
|
|
|
HALASSERT(q < HAL_NUM_TX_QUEUES);
|
|
HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
|
|
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 1<<q);
|
|
for (i = 0; i < 10000; i++) {
|
|
if (ar5211NumTxPending(ah, q) == 0)
|
|
break;
|
|
OS_DELAY(10);
|
|
}
|
|
OS_REG_WRITE(ah, AR_Q_TXD, 0);
|
|
|
|
return (i < 10000);
|
|
}
|
|
|
|
/*
|
|
* Descriptor Access Functions
|
|
*/
|
|
|
|
#define VALID_PKT_TYPES \
|
|
((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
|
|
(1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
|
|
(1<<HAL_PKT_TYPE_BEACON))
|
|
#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
|
|
#define VALID_TX_RATES \
|
|
((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
|
|
(1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
|
|
(1<<0x1d)|(1<<0x18)|(1<<0x1c))
|
|
#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
|
|
|
|
HAL_BOOL
|
|
ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int pktLen,
|
|
u_int hdrLen,
|
|
HAL_PKT_TYPE type,
|
|
u_int txPower,
|
|
u_int txRate0, u_int txTries0,
|
|
u_int keyIx,
|
|
u_int antMode,
|
|
u_int flags,
|
|
u_int rtsctsRate,
|
|
u_int rtsctsDuration,
|
|
u_int compicvLen,
|
|
u_int compivLen,
|
|
u_int comp)
|
|
{
|
|
struct ar5211_desc *ads = AR5211DESC(ds);
|
|
|
|
(void) hdrLen;
|
|
(void) txPower;
|
|
(void) rtsctsRate; (void) rtsctsDuration;
|
|
|
|
HALASSERT(txTries0 != 0);
|
|
HALASSERT(isValidPktType(type));
|
|
HALASSERT(isValidTxRate(txRate0));
|
|
/* XXX validate antMode */
|
|
|
|
ads->ds_ctl0 = (pktLen & AR_FrameLen)
|
|
| (txRate0 << AR_XmitRate_S)
|
|
| (antMode << AR_AntModeXmit_S)
|
|
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
|
|
| (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
|
|
| (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
|
|
| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
|
|
;
|
|
ads->ds_ctl1 = (type << 26)
|
|
| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
|
|
;
|
|
|
|
if (keyIx != HAL_TXKEYIX_INVALID) {
|
|
ads->ds_ctl1 |=
|
|
(keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
|
|
ads->ds_ctl0 |= AR_EncryptKeyValid;
|
|
}
|
|
return AH_TRUE;
|
|
#undef RATE
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int txRate1, u_int txTries1,
|
|
u_int txRate2, u_int txTries2,
|
|
u_int txRate3, u_int txTries3)
|
|
{
|
|
(void) ah; (void) ds;
|
|
(void) txRate1; (void) txTries1;
|
|
(void) txRate2; (void) txTries2;
|
|
(void) txRate3; (void) txTries3;
|
|
return AH_FALSE;
|
|
}
|
|
|
|
void
|
|
ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
|
|
{
|
|
struct ar5211_desc *ads = AR5211DESC(ds);
|
|
|
|
ads->ds_ctl0 |= AR_TxInterReq;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
|
|
const struct ath_desc *ds0)
|
|
{
|
|
struct ar5211_desc *ads = AR5211DESC(ds);
|
|
|
|
HALASSERT((segLen &~ AR_BufLen) == 0);
|
|
|
|
if (firstSeg) {
|
|
/*
|
|
* First descriptor, don't clobber xmit control data
|
|
* setup by ar5211SetupTxDesc.
|
|
*/
|
|
ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
|
|
} else if (lastSeg) { /* !firstSeg && lastSeg */
|
|
/*
|
|
* Last descriptor in a multi-descriptor frame,
|
|
* copy the transmit parameters from the first
|
|
* frame for processing on completion.
|
|
*/
|
|
ads->ds_ctl0 = AR5211DESC_CONST(ds0)->ds_ctl0;
|
|
ads->ds_ctl1 = segLen;
|
|
} else { /* !firstSeg && !lastSeg */
|
|
/*
|
|
* Intermediate descriptor in a multi-descriptor frame.
|
|
*/
|
|
ads->ds_ctl0 = 0;
|
|
ads->ds_ctl1 = segLen | AR_More;
|
|
}
|
|
ads->ds_status0 = ads->ds_status1 = 0;
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Processing of HW TX descriptor.
|
|
*/
|
|
HAL_STATUS
|
|
ar5211ProcTxDesc(struct ath_hal *ah,
|
|
struct ath_desc *ds, struct ath_tx_status *ts)
|
|
{
|
|
struct ar5211_desc *ads = AR5211DESC(ds);
|
|
|
|
if ((ads->ds_status1 & AR_Done) == 0)
|
|
return HAL_EINPROGRESS;
|
|
|
|
/* Update software copies of the HW status */
|
|
ts->ts_seqnum = MS(ads->ds_status1, AR_SeqNum);
|
|
ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
|
|
ts->ts_status = 0;
|
|
if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
|
|
if (ads->ds_status0 & AR_ExcessiveRetries)
|
|
ts->ts_status |= HAL_TXERR_XRETRY;
|
|
if (ads->ds_status0 & AR_Filtered)
|
|
ts->ts_status |= HAL_TXERR_FILT;
|
|
if (ads->ds_status0 & AR_FIFOUnderrun)
|
|
ts->ts_status |= HAL_TXERR_FIFO;
|
|
}
|
|
ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
|
|
ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
|
|
ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
|
|
ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
|
|
ts->ts_virtcol = MS(ads->ds_status0, AR_VirtCollCnt);
|
|
ts->ts_antenna = 0; /* NB: don't know */
|
|
ts->ts_finaltsi = 0;
|
|
/*
|
|
* NB: the number of retries is one less than it should be.
|
|
* Also, 0 retries and 1 retry are both reported as 0 retries.
|
|
*/
|
|
if (ts->ts_shortretry > 0)
|
|
ts->ts_shortretry++;
|
|
if (ts->ts_longretry > 0)
|
|
ts->ts_longretry++;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/*
|
|
* Determine which tx queues need interrupt servicing.
|
|
* STUB.
|
|
*/
|
|
void
|
|
ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
|
|
{
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Retrieve the rate table from the given TX completion descriptor
|
|
*/
|
|
HAL_BOOL
|
|
ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
|
|
{
|
|
return AH_FALSE;
|
|
}
|
|
|