Jeff Roberson 2194393787 Move phys_avail definition into MI code. It is consumed in the MI layer and ... doing so adds more flexibility with less redundant code. Reviewed by: jhb, markj, kib Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D21250		2019-08-16 00:45:14 +00:00
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bcm_bmips_exts.h
bcm_bmips.c	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_bmipsreg.h
bcm_machdep.c	Move phys_avail definition into MI code. It is consumed in the MI layer and	2019-08-16 00:45:14 +00:00
bcm_machdep.h	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_mips74k.c	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_mips74kreg.h	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_mips.c	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_mipsvar.h	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bcm_nvram_cfe.c	bhnd: Implement bhnd(4) platform device registration.	2017-09-27 19:44:23 +00:00
bcm_nvram_cfevar.h	[mips/broadcom]: Early boot NVRAM support	2017-03-23 19:29:12 +00:00
bcm_pmu.c	[mips] [bhnd] Support of old PMU for BMIPS and siba SoC	2017-05-28 12:05:16 +00:00
bcma_nexus.c	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
bhnd_nexus.c	Avoid relying on header pollution from sys/refcount.h.	2019-07-29 20:26:01 +00:00
bhnd_nexusvar.h
files.broadcom	bhnd(4): implement MIPS and PCI(e) interrupt support	2017-11-21 23:15:20 +00:00
siba_nexus.c	bhnd(4): extend the PMU APIs to support bwn(4)	2017-11-22 20:27:46 +00:00
std.broadcom
uart_bus_chipc.c	add snps IP uart support / genaralize UART	2018-08-19 21:10:21 +00:00
uart_cpu_chipc.c