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ARM Coresight is a solution for debug and trace of complex SoC designs. This includes a collection of drivers for ARM Coresight interconnect devices within a small Coresight framework. Supported devices are: o Embedded Trace Macrocell v4 (ETMv4) o Funnel o Dynamic Replicator o Trace Memory Controller (TMC) o CPU debug module Devices are connected to each other internally in SoC and the configuration of each device endpoints is described in FDT. Typical trace flow (as found on Qualcomm Snapdragon 410e): CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM CPU1 -> ETM1 -^ CPU2 -> ETM2 -^ CPU3 -> ETM3 -^ Note that both Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR) are hardware configurations of TMC. This is required for upcoming HWPMC tracing support. This is tested on single-core system only. Reviewed by: andrew (partially) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D14618
59 lines
1.9 KiB
Objective-C
59 lines
1.9 KiB
Objective-C
#-
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# Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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# All rights reserved.
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#
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# This software was developed by SRI International and the University of
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# Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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# ("CTSRD"), as part of the DARPA CRASH research programme.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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# $FreeBSD$
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#
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#include <machine/bus.h>
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#include <arm64/coresight/coresight.h>
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INTERFACE coresight;
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METHOD int init {
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device_t dev;
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};
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METHOD int enable {
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device_t dev;
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struct endpoint *endp;
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struct coresight_event *event;
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};
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METHOD void disable {
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device_t dev;
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struct endpoint *endp;
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struct coresight_event *event;
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};
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METHOD int read {
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device_t dev;
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struct endpoint *endp;
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struct coresight_event *event;
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};
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