116 lines
4.6 KiB
C
116 lines
4.6 KiB
C
/*-
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* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_XDMA_CONTROLLER_PL330_H_
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#define _DEV_XDMA_CONTROLLER_PL330_H_
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/* pl330 registers */
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#define DSR 0x000 /* DMA Manager Status */
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#define DPC 0x004 /* DMA Program Counter */
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#define INTEN 0x020 /* Interrupt Enable */
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#define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */
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#define INTMIS 0x028 /* Interrupt Status */
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#define INTCLR 0x02C /* Interrupt Clear */
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#define FSRD 0x030 /* Fault Status DMA Manager */
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#define FSRC 0x034 /* Fault Status DMA Channel */
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#define FTRD 0x038 /* Fault Type DMA Manager */
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#define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */
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#define CSR(n) (0x100 + 0x08 * (n)) /* Channel status for DMA channel n */
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#define CPC(n) (0x104 + 0x08 * (n)) /* Channel PC for DMA channel n */
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#define SAR(n) (0x400 + 0x20 * (n)) /* Source address for DMA channel n */
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#define DAR(n) (0x404 + 0x20 * (n)) /* Destination address for DMA channel n */
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#define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */
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#define CCR_DST_BURST_SIZE_S 15
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#define CCR_DST_BURST_SIZE_1 (0 << CCR_DST_BURST_SIZE_S)
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#define CCR_DST_BURST_SIZE_2 (1 << CCR_DST_BURST_SIZE_S)
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#define CCR_DST_BURST_SIZE_4 (2 << CCR_DST_BURST_SIZE_S)
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#define CCR_SRC_BURST_SIZE_S 1
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#define CCR_SRC_BURST_SIZE_1 (0 << CCR_SRC_BURST_SIZE_S)
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#define CCR_SRC_BURST_SIZE_2 (1 << CCR_SRC_BURST_SIZE_S)
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#define CCR_SRC_BURST_SIZE_4 (2 << CCR_SRC_BURST_SIZE_S)
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#define CCR_DST_INC (1 << 14)
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#define CCR_SRC_INC (1 << 0)
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#define CCR_DST_PROT_CTRL_S 22
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#define CCR_DST_PROT_PRIV (1 << CCR_DST_PROT_CTRL_S)
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#define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */
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#define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */
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#define DBGSTATUS 0xD00 /* Debug Status */
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#define DBGCMD 0xD04 /* Debug Command */
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#define DBGINST0 0xD08 /* Debug Instruction-0 */
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#define DBGINST1 0xD0C /* Debug Instruction-1 */
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#define CR0 0xE00 /* Configuration Register 0 */
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#define CR1 0xE04 /* Configuration Register 1 */
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#define CR2 0xE08 /* Configuration Register 2 */
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#define CR3 0xE0C /* Configuration Register 3 */
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#define CR4 0xE10 /* Configuration Register 4 */
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#define CRD 0xE14 /* DMA Configuration */
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#define WD 0xE80 /* Watchdog Register */
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#define R_SAR 0
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#define R_CCR 1
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#define R_DAR 2
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/*
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* 0xFE0- 0xFEC periph_id_n RO Configuration-dependent Peripheral Identification Registers
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* 0xFF0- 0xFFC pcell_id_n RO Configuration-dependent Component Identification Registers
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*/
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/* pl330 ISA */
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#define DMAADDH 0x54
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#define DMAADNH 0x5c
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#define DMAEND 0x00
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#define DMAFLUSHP 0x35
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#define DMAGO 0xa0
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#define DMAKILL 0x01
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#define DMALD 0x04
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#define DMALDP 0x25
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#define DMALP 0x20
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#define DMALPEND 0x28
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#define DMALPEND_NF (1 << 4) /* DMALP started the loop */
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/*
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* TODO: documentation miss opcode for infinite loop
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* #define DMALPFE 0
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*/
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#define DMAMOV 0xbc
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#define DMANOP 0x18
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#define DMARMB 0x12
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#define DMASEV 0x34
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#define DMAST 0x08
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#define DMASTP 0x29
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#define DMASTZ 0x0c
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#define DMAWFE 0x36
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#define DMAWFP 0x30
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#define DMAWMB 0x13
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#endif /* !_DEV_XDMA_CONTROLLER_PL330_H_ */
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