110 lines
3.9 KiB
C
110 lines
3.9 KiB
C
/*-
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* Copyright (C) 2009 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Samsung S3C2440X processor is ARM920T based integrated CPU
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*
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* Reference:
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* S3C2440A/S3C2442B User's Manual
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*/
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#ifndef _ARM_S3C2XX0_S3C2440REG_H_
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#define _ARM_S3C2XX0_S3C2440REG_H_
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/* common definitions for S3C2410 and S3C2440 */
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#include <arm/samsung/s3c2xx0/s3c24x0reg.h>
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/*
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* Memory Map
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*/
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#define S3C2440_BANK_SIZE 0x08000000
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#define S3C2440_BANK_START(n) (S3C2410_BANK_SIZE*(n))
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#define S3C2440_SDRAM_START S3C2410_BANK_START(6)
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/* interrupt control */
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#define S3C2440_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10)
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/* Clock control */
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/* CLKMAN_CLKCON */
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#define S3C2440_CLKCON_STOP (1<<0) /* 1=transition to STOP mode */
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/* CLKMAN_CLKDIVN */
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#define S3C2440_CLKDIVN_HDIVN (3<<1) /* hclk */
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#define S3C2440_CLKMAN_CAMDIVN 0x18
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#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
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#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
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/* NAND Flash controller */
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#define S3C2440_NANDFC_SIZE 0x40
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#define S3C2440_NANDFC_NFCONT 0x04
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#define S3C2440_NFCONT_LOCK_TIGHT (1<<13) /* Lock part of the NAND */
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#define S3C2440_NFCONT_SOFT_LOCK (1<<12) /* Soft lock part of the NAND */
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#define S3C2440_NFCONT_ILLEGAL_ACC_INT (1<<10) /* Illegal access interrupt */
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#define S3C2440_NFCONT_RNB_INT (1<<9) /* RnB transition interrupt */
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#define S3C2440_NFCONT_RNB_TRANS_MODE (1<<8) /* RnB transition mode */
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#define S3C2440_NFCONT_SPARE_ECC_LOCK (1<<6) /* Lock spare ECC generation */
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#define S3C2440_NFCONT_MAIN_ECC_LOCK (1<<5) /* Lock main ECC generation */
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#define S3C2440_NFCONT_INIT_ECC (1<<4) /* Init ECC encoder/decoder */
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#define S3C2440_NFCONT_NCE (1<<1) /* NAND Chip select */
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#define S3C2440_NFCONT_ENABLE (1<<0) /* Enable the controller */
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#define S3C2440_NANDFC_NFCMMD 0x08
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#define S3C2440_NANDFC_NFADDR 0x0c
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#define S3C2440_NANDFC_NFDATA 0x10
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#define S3C2440_NANDFC_NFSTAT 0x20
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/* MMC/SD */
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/* SDI_CON */
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#define S3C2440_CON_RESET (1<<8)
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#define S3C2440_CON_CLOCK_TYPE (1<<5)
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/* SDI_FSTA */
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#define S3c2440_FSTA_RESET (1<<16)
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#define S3C2440_FSTA_FAIL_ERROR_MSK (3<<14)
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#define S3C2440_FSTA_FAIL_NONE (0<<14)
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#define S3C2440_FSTA_FAIL_FIFO (1<<14)
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#define S3C2440_FSTA_FAIL_LAST_TRANS (2<<14)
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/* GPIO */
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#define S3C2440_GPIO_SIZE 0xd0
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/* SD interface */
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#define S3C2410_SDI_SIZE 0x44
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#define DCON_START (1<<14) /* Start the data transfer */
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#define S3C2440_SDI_IMSK 0x3c /* Interrupt mask */
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#define S3C2440_SDI_IMASK_ALL 0x3C7C0
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#define S3C2440_SDI_DAT 0x40
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/* ADC */
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#define ADCTSC_UD_SEN (1<<8)
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#define S3C2440_ADC_SIZE 0x18
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/* UART */
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#define S3C2440_UFSTAT_TXCOUNT (0x3f << 8)
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#define S3C2440_UFSTAT_RXCOUNT (0x3f << 0)
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#endif /* _ARM_S3C2XX0_S3C2440REG_H_ */
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