f43581345b
Rework the timeout code to use actual time rather than a DELAY() loop and to use both typical and maximum to allow logging of timeout failures. Also correct the erase timeout, it is specified in milliseconds not microseconds like the other timeouts. Do not invoke DELAY() between status queries as this adds significant latency which in turn reduced write performance substantially. Sanity check timeout values from the hardware. Implement support for buffered writes (only enabled on Intel/Sharp parts for now). This yields an order of magnitude speedup on the 64MB Intel StrataFlash parts we use. When making a copy of the block to modify, also keep a clean copy around until we are ready to commit the block and use it to avoid unnecessary erases. In the non-buffer write case, also use it to avoid unnecessary writes when the block has not been erased. This yields a significant speedup when doing things like zeroing a block. Sponsored by: DARPA, AFRL Reviewed by: imp (previous version)
153 lines
6.0 KiB
C
153 lines
6.0 KiB
C
/*-
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* Copyright (c) 2007, Juniper Networks, Inc.
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* Copyright (c) 2012-2013, SRI International
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
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* programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_CFI_REG_H_
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#define _DEV_CFI_REG_H_
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struct cfi_qry {
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u_char reserved[16];
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u_char ident[3]; /* "QRY" */
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u_char pri_vend[2];
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u_char pri_vend_eqt[2];
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u_char alt_vend[2];
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u_char alt_vend_eqt[2];
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/* System Interface Information. */
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u_char min_vcc;
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u_char max_vcc;
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u_char min_vpp;
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u_char max_vpp;
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u_char tto_byte_write; /* 2**n microseconds. */
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u_char tto_buf_write; /* 2**n microseconds. */
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u_char tto_block_erase; /* 2**n milliseconds. */
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u_char tto_chip_erase; /* 2**n milliseconds. */
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u_char mto_byte_write; /* 2**n times typical t/o. */
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u_char mto_buf_write; /* 2**n times typical t/o. */
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u_char mto_block_erase; /* 2**n times typical t/o. */
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u_char mto_chip_erase; /* 2**n times typical t/o. */
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/* Device Geometry Definition. */
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u_char size; /* 2**n bytes. */
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u_char iface[2];
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u_char max_buf_write_size[2]; /* 2**n. */
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u_char nregions; /* Number of erase regions. */
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u_char region[4]; /* Single entry. */
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/* Additional entries follow. */
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/* Primary Vendor-specific Extended Query table follows. */
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/* Alternate Vendor-specific Extended Query table follows. */
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};
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#define CFI_QRY_CMD_ADDR 0x55
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#define CFI_QRY_CMD_DATA 0x98
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#define CFI_QRY_IDENT offsetof(struct cfi_qry, ident)
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#define CFI_QRY_VEND offsetof(struct cfi_qry, pri_vend)
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#define CFI_QRY_TTO_WRITE offsetof(struct cfi_qry, tto_byte_write)
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#define CFI_QRY_TTO_BUFWRITE offsetof(struct cfi_qry, tto_buf_write)
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#define CFI_QRY_TTO_ERASE offsetof(struct cfi_qry, tto_block_erase)
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#define CFI_QRY_MTO_WRITE offsetof(struct cfi_qry, mto_byte_write)
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#define CFI_QRY_MTO_BUFWRITE offsetof(struct cfi_qry, mto_buf_write)
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#define CFI_QRY_MTO_ERASE offsetof(struct cfi_qry, mto_block_erase)
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#define CFI_QRY_SIZE offsetof(struct cfi_qry, size)
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#define CFI_QRY_IFACE offsetof(struct cfi_qry, iface)
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#define CFI_QRY_MAXBUF offsetof(struct cfi_qry, max_buf_write_size)
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#define CFI_QRY_NREGIONS offsetof(struct cfi_qry, nregions)
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#define CFI_QRY_REGION0 offsetof(struct cfi_qry, region)
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#define CFI_QRY_REGION(x) (CFI_QRY_REGION0 + (x) * 4)
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#define CFI_VEND_NONE 0x0000
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#define CFI_VEND_INTEL_ECS 0x0001
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#define CFI_VEND_AMD_SCS 0x0002
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#define CFI_VEND_INTEL_SCS 0x0003
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#define CFI_VEND_AMD_ECS 0x0004
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#define CFI_VEND_MITSUBISHI_SCS 0x0100
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#define CFI_VEND_MITSUBISHI_ECS 0x0101
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#define CFI_IFACE_X8 0x0000
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#define CFI_IFACE_X16 0x0001
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#define CFI_IFACE_X8X16 0x0002
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#define CFI_IFACE_X32 0x0003
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#define CFI_IFACE_X16X32 0x0005
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/* Standard Command Set (aka Basic Command Set) */
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#define CFI_BCS_BLOCK_ERASE 0x20
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#define CFI_BCS_PROGRAM 0x40
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#define CFI_BCS_CLEAR_STATUS 0x50
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#define CFI_BCS_READ_STATUS 0x70
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#define CFI_BCS_ERASE_SUSPEND 0xb0
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#define CFI_BCS_ERASE_RESUME 0xd0 /* Equals CONFIRM */
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#define CFI_BCS_CONFIRM 0xd0
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#define CFI_BCS_BUF_PROG_SETUP 0xe8
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#define CFI_BCS_READ_ARRAY 0xff
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/* Intel commands. */
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#define CFI_INTEL_LB 0x01 /* Lock Block */
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#define CFI_INTEL_LBS 0x60 /* Lock Block Setup */
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#define CFI_INTEL_READ_ID 0x90 /* Read Identifier */
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#define CFI_INTEL_PP_SETUP 0xc0 /* Protection Program Setup */
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#define CFI_INTEL_UB 0xd0 /* Unlock Block */
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/* NB: these are addresses for 16-bit accesses */
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#define CFI_INTEL_PLR 0x80 /* Protection Lock Register */
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#define CFI_INTEL_PR(n) (0x81+(n)) /* Protection Register */
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/* Status register definitions */
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#define CFI_INTEL_STATUS_WSMS 0x0080 /* Write Machine Status */
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#define CFI_INTEL_STATUS_ESS 0x0040 /* Erase Suspend Status */
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#define CFI_INTEL_STATUS_ECLBS 0x0020 /* Erase and Clear Lock-Bit Status */
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#define CFI_INTEL_STATUS_PSLBS 0x0010 /* Program and Set Lock-Bit Status */
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#define CFI_INTEL_STATUS_VPENS 0x0008 /* Programming Voltage Status */
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#define CFI_INTEL_STATUS_PSS 0x0004 /* Program Suspend Status */
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#define CFI_INTEL_STATUS_DPS 0x0002 /* Device Protect Status */
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#define CFI_INTEL_STATUS_RSVD 0x0001 /* reserved */
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/* eXtended Status register definitions */
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#define CFI_INTEL_XSTATUS_WBS 0x8000 /* Write Buffer Status */
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#define CFI_INTEL_XSTATUS_RSVD 0x7f00 /* reserved */
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/* AMD commands. */
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#define CFI_AMD_BLOCK_ERASE 0x30
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#define CFI_AMD_UNLOCK_ACK 0x55
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#define CFI_AMD_ERASE_SECTOR 0x80
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#define CFI_AMD_PROGRAM 0xa0
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#define CFI_AMD_UNLOCK 0xaa
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#define AMD_ADDR_START 0xaaa
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#define AMD_ADDR_ACK 0x555
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#endif /* _DEV_CFI_REG_H_ */
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