477a642cee
There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/*
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* Kernel interface to machine-dependent clock driver.
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* Garrett Wollman, September 1994.
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* This file is in the public domain.
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*
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* $Id: clock.h,v 1.24 1997/02/22 09:33:59 peter Exp $
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*/
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#ifndef _MACHINE_CLOCK_H_
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#define _MACHINE_CLOCK_H_
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#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
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#define CPU_CLOCKUPDATE(otime, ntime) cpu_clockupdate((otime), (ntime))
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#else
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#define CPU_CLOCKUPDATE(otime, ntime) (*(otime) = *(ntime))
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#endif
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#define CPU_THISTICKLEN(dflt) dflt
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#define I586_CTR_COMULTIPLIER_SHIFT 20
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#define I586_CTR_MULTIPLIER_SHIFT 32
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#ifdef KERNEL
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/*
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* i386 to clock driver interface.
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* XXX almost all of it is misplaced. i586 stuff is done in isa/clock.c
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* and isa stuff is done in i386/microtime.s and i386/support.s.
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*/
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extern int adjkerntz;
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extern int disable_rtc_set;
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#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
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extern u_int i586_ctr_bias;
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extern u_int i586_ctr_comultiplier;
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extern u_int i586_ctr_freq;
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extern u_int i586_ctr_multiplier;
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#endif
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extern int statclock_disable;
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extern u_int timer_freq;
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extern int timer0_max_count;
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extern u_int timer0_overflow_threshold;
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extern u_int timer0_prescaler_count;
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extern int wall_cmos_clock;
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/*
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* Driver to clock driver interface.
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*/
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struct clockframe;
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void DELAY __P((int usec));
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int acquire_timer0 __P((int rate,
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void (*function)(struct clockframe *frame)));
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int acquire_timer2 __P((int mode));
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int release_timer0 __P((void));
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int release_timer2 __P((void));
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#ifndef PC98
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int rtcin __P((int val));
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#else
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int acquire_timer1 __P((int mode));
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int release_timer1 __P((void));
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#endif
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int sysbeep __P((int pitch, int period));
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#ifdef CLOCK_HAIR
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#ifdef PC98
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#include <pc98/pc98/pc98.h> /* XXX */
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#else
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#include <i386/isa/isa.h> /* XXX */
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#endif
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#include <i386/isa/timerreg.h> /* XXX */
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static __inline u_int
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clock_latency(void)
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{
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u_char high, low;
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outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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return (timer0_prescaler_count + timer0_max_count
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- ((high << 8) | low));
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}
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#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
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/*
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* When we update `time', on i586's we also update `i586_ctr_bias'
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* atomically. `i586_ctr_bias' is the best available approximation to
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* the value of the i586 counter (mod 2^32) at the time of the i8254
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* counter transition that caused the clock interrupt that caused the
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* update. clock_latency() gives the time between the transition and
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* the update to within a few usec provided another such transition
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* hasn't occurred. We don't bother checking for counter overflow as
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* in microtime(), since if it occurs then we're close to losing clock
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* interrupts.
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*/
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static __inline void
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cpu_clockupdate(volatile struct timeval *otime, struct timeval *ntime)
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{
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if (i586_ctr_freq != 0) {
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u_int i586_count; /* truncated */
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u_int i8254_count;
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disable_intr();
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i8254_count = clock_latency();
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i586_count = rdtsc();
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i586_ctr_bias = i586_count
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- (u_int)
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(((unsigned long long)i586_ctr_comultiplier
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* i8254_count)
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>> I586_CTR_COMULTIPLIER_SHIFT);
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*otime = *ntime;
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enable_intr();
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} else
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*otime = *ntime;
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}
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#endif /* I586_CPU || I686_CPU */
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#endif /* CLOCK_HAIR */
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#endif /* KERNEL */
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#endif /* !_MACHINE_CLOCK_H_ */
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