caf552a607
It appears we must read MIB values as 2 4-byte words, lower address first. A single 8-byte MIB read returns the value with the lower 4 bytes copied into the upper 4 bytes, resulting in bogus byte counter values. Reviewed by: mw MFC after: 2 weeks Sponsored by: Rubicon Communications, LLC (Netgate) Differential Revision: https://reviews.freebsd.org/D27870
328 lines
8.0 KiB
C
328 lines
8.0 KiB
C
/*
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* Copyright (c) 2017 Stormshield.
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* Copyright (c) 2017 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _IF_MVNETAVAR_H_
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#define _IF_MVNETAVAR_H_
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#include <net/if.h>
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#define MVNETA_HWHEADER_SIZE 2 /* Marvell Header */
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#define MVNETA_ETHER_SIZE 22 /* Maximum ether size */
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#define MVNETA_A370_MAX_CSUM_MTU 1600 /* Max frame len for TX csum */
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#define MVNETA_A3700_MAX_CSUM_MTU 9600
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#define MVNETA_MAX_FRAME (MJUM9BYTES)
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/*
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* Default limit of queue length
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*
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* queue 0 is lowest priority and queue 7 is highest priority.
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* IP packet is received on queue 7 by default.
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*/
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#define MVNETA_TX_RING_CNT 512
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#define MVNETA_RX_RING_CNT 256
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#define MVNETA_BUFRING_SIZE 1024
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#define MVNETA_PACKET_OFFSET 64
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#define MVNETA_RXTH_COUNT 128
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#define MVNETA_RX_REFILL_COUNT 8
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#define MVNETA_TX_RECLAIM_COUNT 32
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/*
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* Device Register access
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*/
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#define MVNETA_READ(sc, reg) \
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bus_read_4((sc)->res[0], (reg))
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#define MVNETA_WRITE(sc, reg, val) \
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bus_write_4((sc)->res[0], (reg), (val))
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#define MVNETA_READ_REGION(sc, reg, val, c) \
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bus_read_region_4((sc)->res[0], (reg), (val), (c))
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#define MVNETA_WRITE_REGION(sc, reg, val, c) \
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bus_write_region_4((sc)->res[0], (reg), (val), (c))
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#define MVNETA_READ_MIB(sc, reg) \
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bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))
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#define MVNETA_IS_LINKUP(sc) \
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(MVNETA_READ((sc), MVNETA_PSR) & MVNETA_PSR_LINKUP)
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#define MVNETA_IS_QUEUE_SET(queues, q) \
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((((queues) >> (q)) & 0x1))
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/*
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* EEE: Lower Power Idle config
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* Default timer is duration of MTU sized frame transmission.
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* The timer can be negotiated by LLDP protocol, but we have no
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* support.
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*/
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#define MVNETA_LPI_TS (ETHERMTU * 8 / 1000) /* [us] */
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#define MVNETA_LPI_TW (ETHERMTU * 8 / 1000) /* [us] */
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#define MVNETA_LPI_LI (ETHERMTU * 8 / 1000) /* [us] */
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/*
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* DMA Descriptor
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*
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* the ethernet device has 8 rx/tx DMA queues. each of queue has its own
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* decriptor list. descriptors are simply index by counter inside the device.
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*/
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#define MVNETA_TX_SEGLIMIT 32
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#define MVNETA_QUEUE_IDLE 1
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#define MVNETA_QUEUE_WORKING 2
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#define MVNETA_QUEUE_DISABLED 3
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struct mvneta_buf {
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struct mbuf * m; /* pointer to related mbuf */
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bus_dmamap_t dmap;
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};
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struct mvneta_rx_ring {
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int queue_status;
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/* Real descriptors array. shared by RxDMA */
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struct mvneta_rx_desc *desc;
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bus_dmamap_t desc_map;
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bus_addr_t desc_pa;
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/* Virtual address of the RX buffer */
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void *rxbuf_virt_addr[MVNETA_RX_RING_CNT];
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/* Managment entries for each of descritors */
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struct mvneta_buf rxbuf[MVNETA_RX_RING_CNT];
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/* locks */
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struct mtx ring_mtx;
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/* Index */
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int dma;
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int cpu;
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/* Limit */
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int queue_th_received;
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int queue_th_time; /* [Tclk] */
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/* LRO */
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struct lro_ctrl lro;
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boolean_t lro_enabled;
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/* Is this queue out of mbuf */
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boolean_t needs_refill;
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} __aligned(CACHE_LINE_SIZE);
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struct mvneta_tx_ring {
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/* Index of this queue */
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int qidx;
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/* IFNET pointer */
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struct ifnet *ifp;
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/* Ring buffer for IFNET */
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struct buf_ring *br;
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/* Real descriptors array. shared by TxDMA */
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struct mvneta_tx_desc *desc;
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bus_dmamap_t desc_map;
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bus_addr_t desc_pa;
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/* Managment entries for each of descritors */
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struct mvneta_buf txbuf[MVNETA_TX_RING_CNT];
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/* locks */
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struct mtx ring_mtx;
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/* Index */
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int used;
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int dma;
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int cpu;
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/* watchdog */
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#define MVNETA_WATCHDOG_TXCOMP (hz / 10) /* 100ms */
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#define MVNETA_WATCHDOG (10 * hz) /* 10s */
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int watchdog_time;
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int queue_status;
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boolean_t queue_hung;
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/* Task */
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struct task task;
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struct taskqueue *taskq;
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/* Stats */
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uint32_t drv_error;
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} __aligned(CACHE_LINE_SIZE);
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static __inline int
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tx_counter_adv(int ctr, int n)
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{
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ctr += n;
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while (__predict_false(ctr >= MVNETA_TX_RING_CNT))
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ctr -= MVNETA_TX_RING_CNT;
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return (ctr);
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}
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static __inline int
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rx_counter_adv(int ctr, int n)
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{
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ctr += n;
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while (__predict_false(ctr >= MVNETA_RX_RING_CNT))
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ctr -= MVNETA_RX_RING_CNT;
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return (ctr);
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}
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/*
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* Timeout control
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*/
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#define MVNETA_PHY_TIMEOUT 10000 /* msec */
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#define RX_DISABLE_TIMEOUT 0x1000000 /* times */
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#define TX_DISABLE_TIMEOUT 0x1000000 /* times */
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#define TX_FIFO_EMPTY_TIMEOUT 0x1000000 /* times */
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/*
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* Debug
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*/
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#define KASSERT_SC_MTX(sc) \
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KASSERT(mtx_owned(&(sc)->mtx), ("SC mutex not owned"))
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#define KASSERT_BM_MTX(sc) \
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KASSERT(mtx_owned(&(sc)->bm.bm_mtx), ("BM mutex not owned"))
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#define KASSERT_RX_MTX(sc, q) \
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KASSERT(mtx_owned(&(sc)->rx_ring[(q)].ring_mtx),\
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("RX mutex not owned"))
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#define KASSERT_TX_MTX(sc, q) \
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KASSERT(mtx_owned(&(sc)->tx_ring[(q)].ring_mtx),\
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("TX mutex not owned"))
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/*
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* sysctl(9) parameters
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*/
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struct mvneta_sysctl_queue {
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struct mvneta_softc *sc;
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int rxtx;
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int queue;
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};
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#define MVNETA_SYSCTL_RX 0
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#define MVNETA_SYSCTL_TX 1
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struct mvneta_sysctl_mib {
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struct mvneta_softc *sc;
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int index;
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uint64_t counter;
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};
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enum mvneta_phy_mode {
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MVNETA_PHY_QSGMII,
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MVNETA_PHY_SGMII,
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MVNETA_PHY_RGMII,
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MVNETA_PHY_RGMII_ID
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};
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/*
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* Ethernet Device main context
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*/
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DECLARE_CLASS(mvneta_driver);
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struct mvneta_softc {
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device_t dev;
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uint32_t version;
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/*
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* mtx must be held by interface functions to/from
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* other frameworks. interrupt hander, sysctl hander,
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* ioctl hander, and so on.
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*/
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struct mtx mtx;
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struct resource *res[2];
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void *ih_cookie[1];
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struct ifnet *ifp;
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uint32_t mvneta_if_flags;
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uint32_t mvneta_media;
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uint32_t tx_csum_limit;
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uint32_t rx_frame_size;
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int phy_attached;
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enum mvneta_phy_mode phy_mode;
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int phy_addr;
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int phy_speed; /* PHY speed */
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boolean_t phy_fdx; /* Full duplex mode */
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boolean_t autoneg; /* Autonegotiation status */
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boolean_t use_inband_status; /* In-band link status */
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/*
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* Link State control
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*/
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boolean_t linkup;
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device_t miibus;
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struct mii_data *mii;
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uint8_t enaddr[ETHER_ADDR_LEN];
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struct ifmedia mvneta_ifmedia;
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bus_dma_tag_t rx_dtag;
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bus_dma_tag_t rxbuf_dtag;
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bus_dma_tag_t tx_dtag;
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bus_dma_tag_t txmbuf_dtag;
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struct mvneta_rx_ring rx_ring[MVNETA_RX_QNUM_MAX];
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struct mvneta_tx_ring tx_ring[MVNETA_TX_QNUM_MAX];
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/*
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* Maintance clock
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*/
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struct callout tick_ch;
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int cf_lpi;
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int cf_fc;
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int debug;
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/*
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* Sysctl interfaces
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*/
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struct mvneta_sysctl_queue sysctl_rx_queue[MVNETA_RX_QNUM_MAX];
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struct mvneta_sysctl_queue sysctl_tx_queue[MVNETA_TX_QNUM_MAX];
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/*
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* MIB counter
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*/
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struct mvneta_sysctl_mib sysctl_mib[MVNETA_PORTMIB_NOCOUNTER];
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uint64_t counter_pdfc;
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uint64_t counter_pofc;
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uint32_t counter_watchdog; /* manual reset when clearing mib */
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uint32_t counter_watchdog_mib; /* reset after each mib update */
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};
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#define MVNETA_RX_RING(sc, q) \
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(&(sc)->rx_ring[(q)])
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#define MVNETA_TX_RING(sc, q) \
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(&(sc)->tx_ring[(q)])
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int mvneta_attach(device_t);
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#ifdef FDT
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int mvneta_fdt_mac_address(struct mvneta_softc *, uint8_t *);
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#endif
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#endif /* _IF_MVNETAVAR_H_ */
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