4c38c193d4
Without disabling interrupts it's possible for another thread to preempt and update the registers post-read (tlb1_read_entry) or pre-write (tlb1_write_entry), and confuse the kernel with mixed register states. MFC after: 2 weeks |
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aim | ||
booke | ||
conf | ||
cpufreq | ||
fpu | ||
include | ||
mambo | ||
mikrotik | ||
mpc85xx | ||
ofw | ||
powermac | ||
powerpc | ||
ps3 | ||
pseries | ||
psim |