andrew afaafc8bde Use 4 levels of page tables when enabling the MMU. This will allow us to ...

boot on an SoC that places physical memory at an address past where three
levels of page tables can access in an identity mapping.

Submitted by:   Wojciech Macek <wma@semihalf.com>,
                Patrick Wildt <patrick@bitrig.org>
Differential Revision:	https://reviews.freebsd.org/D3885 (partial)
Differential Revision:	https://reviews.freebsd.org/D3744

2015-10-19 13:20:23 +00:00

..

acpica

Add ARM64TODO comments to ACPI PCI stubs

2015-07-12 18:32:16 +00:00

arm64

Use 4 levels of page tables when enabling the MMU. This will allow us to

2015-10-19 13:20:23 +00:00

cavium

arm64 ThunderX PCIe workaround: enumerate only one slot for now

2015-09-22 12:56:34 +00:00

conf

Add ThunderX VNIC to arm64/GENERIC kernel

2015-10-18 22:13:21 +00:00

include

Use 4 levels of page tables when enabling the MMU. This will allow us to

2015-10-19 13:20:23 +00:00