ebda8d9db8
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156 lines
5.7 KiB
C
156 lines
5.7 KiB
C
/******************************************************************************
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SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2001-2017, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IXGBE_DCB_82599_H_
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#define _IXGBE_DCB_82599_H_
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/* DCB register definitions */
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#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
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* 1 WSP - Weighted Strict Priority
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*/
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#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
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* 1 WRR - Weighted Round Robin
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*/
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#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
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#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
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* clear!
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*/
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#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
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/* Receive UP2TC mapping */
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#define IXGBE_RTRUP2TC_UP_SHIFT 3
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#define IXGBE_RTRUP2TC_UP_MASK 7
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/* Transmit UP2TC mapping */
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#define IXGBE_RTTUP2TC_UP_SHIFT 3
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#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */
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#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
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#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
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* buffers enable
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*/
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
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* (RSS) enable
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*/
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/* RTRPCS Bit Masks */
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#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
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/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
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#define IXGBE_RTRPCS_RAC 0x00000004
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#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */
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/* RTTDT2C Bit Masks */
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#define IXGBE_RTTDT2C_MCL_SHIFT 12
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#define IXGBE_RTTDT2C_BWG_SHIFT 9
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#define IXGBE_RTTDT2C_GSP 0x40000000
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#define IXGBE_RTTDT2C_LSP 0x80000000
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#define IXGBE_RTTPT2C_MCL_SHIFT 12
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#define IXGBE_RTTPT2C_BWG_SHIFT 9
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#define IXGBE_RTTPT2C_GSP 0x40000000
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#define IXGBE_RTTPT2C_LSP 0x80000000
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/* RTTPCS Bit Masks */
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#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,
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* 1 SP - Strict Priority
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*/
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#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_RTTPCS_ARBD_SHIFT 22
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#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
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#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
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/* SECTXMINIFG DCB */
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#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */
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/* BCN register definitions */
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#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
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#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
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#define IXGBE_RTTBCNCR_MNG_CMTGI 0x00000001
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#define IXGBE_RTTBCNCR_MGN_BCNA_MODE 0x00000002
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#define IXGBE_RTTBCNCR_RSV7_11_SHIFT 5
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#define IXGBE_RTTBCNCR_G 0x00000400
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#define IXGBE_RTTBCNCR_I 0x00000800
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#define IXGBE_RTTBCNCR_H 0x00001000
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#define IXGBE_RTTBCNCR_VER_SHIFT 14
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#define IXGBE_RTTBCNCR_CMT_ETH_SHIFT 16
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#define IXGBE_RTTBCNACL_SMAC_L_SHIFT 16
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#define IXGBE_RTTBCNTG_BCNA_MODE 0x80000000
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#define IXGBE_RTTBCNRTT_TS_SHIFT 3
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#define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT 16
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#define IXGBE_RTTBCNRD_BCN_CLEAR_ALL 0x00000002
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#define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT 2
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#define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT 16
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#define IXGBE_RTTBCNRD_DRIFT_ENA 0x80000000
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/* DCB driver APIs */
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/* DCB PFC */
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *);
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/* DCB stats */
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s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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/* DCB config arbiters */
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s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *);
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s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *, u8 *);
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s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *,
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u8 *, u8 *);
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/* DCB initialization */
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s32 ixgbe_dcb_config_82599(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *,
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u8 *, u8 *);
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#endif /* _IXGBE_DCB_82959_H_ */
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