f785676f2a
all of the features in the current working draft of the upcoming C++ standard, provisionally named C++1y. The code generator's performance is greatly increased, and the loop auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The PowerPC backend has made several major improvements to code generation quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ backends have all seen major feature work. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.4/docs/ReleaseNotes.html> <http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html> MFC after: 1 month
122 lines
5.5 KiB
TableGen
122 lines
5.5 KiB
TableGen
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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include "MipsSchedule.td"
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include "MipsInstrInfo.td"
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include "MipsCallingConv.td"
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def MipsInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide.">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers.">;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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"Enable o32 ABI">;
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def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
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"Enable n32 ABI">;
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def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
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"Enable n64 ABI">;
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def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
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"Enable eabi ABI">;
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions.">;
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def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
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"Enable 'signext in register' instructions.">;
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def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
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"Enable 'conditional move' instructions.">;
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def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
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"Enable 'byte/half swap' instructions.">;
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def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
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"Enable 'count leading bits' instructions.">;
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def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true",
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"Enable 'FP indexed load/store' instructions.">;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureCondMov, FeatureBitCount]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips32, FeatureSEInReg, FeatureSwap,
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FeatureFPIdx]>;
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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[FeatureGP64Bit, FeatureFP64Bit,
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FeatureMips32, FeatureFPIdx]>;
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def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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"Mips64r2", "Mips64r2 ISA Support",
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[FeatureMips64, FeatureMips32r2]>;
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def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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"Mips16 mode">;
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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"Mips DSP-R2 ASE", [FeatureDSP]>;
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def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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"microMips mode">;
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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def : Proc<"mips32", [FeatureMips32]>;
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def : Proc<"mips32r2", [FeatureMips32r2]>;
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def : Proc<"mips64", [FeatureMips64]>;
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def : Proc<"mips64r2", [FeatureMips64r2]>;
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def : Proc<"mips16", [FeatureMips16]>;
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def MipsAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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def MipsAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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let MnemonicContainsDot = 1;
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}
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def MipsAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Recognize hard coded registers.
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string RegisterPrefix = "$";
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}
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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let AssemblyParsers = [MipsAsmParser];
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let AssemblyWriters = [MipsAsmWriter];
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let AssemblyParserVariants = [MipsAsmParserVariant];
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}
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