a8692c16c9
riscv cores. GFE cores come with standard DTS file that lacks standard 'dmas =' property, which means xae(4) could not find a DMA controller to use. The 'dmas' property could not be added to the DTS file because the ethernet controller and DMA engine parts in Linux are implemented in a single driver. Instead of 'dmas' property the standard Xilinx 'axistream-connected' property is provided, so fallback to use it instead. Suggested by: James Clarke <jrtc27@jrtc27.com> Reviewed by: James Clarke <jrtc27@jrtc27.com> Sponsored by: DARPA, AFRL
97 lines
4.1 KiB
C
97 lines
4.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_XILINX_AXIDMA_H_
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#define _DEV_XILINX_AXIDMA_H_
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#define AXI_DMACR(n) (0x00 + 0x30 * (n)) /* DMA Control register */
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#define DMACR_RS (1 << 0) /* Run / Stop. */
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#define DMACR_RESET (1 << 2) /* Soft reset the AXI DMA core. */
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#define DMACR_IOC_IRQEN (1 << 12) /* Interrupt on Complete (IOC) Interrupt Enable. */
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#define DMACR_DLY_IRQEN (1 << 13) /* Interrupt on Delay Timer Interrupt Enable. */
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#define DMACR_ERR_IRQEN (1 << 14) /* Interrupt on Error Interrupt Enable. */
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#define AXI_DMASR(n) (0x04 + 0x30 * (n)) /* DMA Status register */
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#define DMASR_HALTED (1 << 0)
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#define DMASR_IDLE (1 << 1)
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#define DMASR_SGINCLD (1 << 3) /* Scatter Gather Enabled */
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#define DMASR_DMAINTERR (1 << 4) /* DMA Internal Error. */
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#define DMASR_DMASLVERR (1 << 5) /* DMA Slave Error. */
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#define DMASR_DMADECOREERR (1 << 6) /* Decode Error. */
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#define DMASR_SGINTERR (1 << 8) /* Scatter Gather Internal Error. */
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#define DMASR_SGSLVERR (1 << 9) /* Scatter Gather Slave Error. */
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#define DMASR_SGDECERR (1 << 10) /* Scatter Gather Decode Error. */
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#define DMASR_IOC_IRQ (1 << 12) /* Interrupt on Complete. */
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#define DMASR_DLY_IRQ (1 << 13) /* Interrupt on Delay. */
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#define DMASR_ERR_IRQ (1 << 14) /* Interrupt on Error. */
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#define AXI_CURDESC(n) (0x08 + 0x30 * (n)) /* Current Descriptor Pointer. Lower 32 bits of the address. */
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#define AXI_CURDESC_MSB(n) (0x0C + 0x30 * (n)) /* Current Descriptor Pointer. Upper 32 bits of address. */
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#define AXI_TAILDESC(n) (0x10 + 0x30 * (n)) /* Tail Descriptor Pointer. Lower 32 bits. */
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#define AXI_TAILDESC_MSB(n) (0x14 + 0x30 * (n)) /* Tail Descriptor Pointer. Upper 32 bits of address. */
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#define AXI_SG_CTL 0x2C /* Scatter/Gather User and Cache */
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#define AXIDMA_NCHANNELS 2
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#define AXIDMA_DESCS_NUM 512
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#define AXIDMA_TX_CHAN 0
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#define AXIDMA_RX_CHAN 1
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struct axidma_desc {
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uint32_t next;
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uint32_t reserved1;
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uint32_t phys;
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uint32_t reserved2;
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uint32_t reserved3;
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uint32_t reserved4;
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uint32_t control;
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#define BD_CONTROL_TXSOF (1 << 27) /* Start of Frame. */
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#define BD_CONTROL_TXEOF (1 << 26) /* End of Frame. */
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#define BD_CONTROL_LEN_S 0 /* Buffer Length. */
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#define BD_CONTROL_LEN_M (0x3ffffff << BD_CONTROL_LEN_S)
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uint32_t status;
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#define BD_STATUS_CMPLT (1 << 31)
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#define BD_STATUS_TRANSFERRED_S 0
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#define BD_STATUS_TRANSFERRED_M (0x7fffff << BD_STATUS_TRANSFERRED_S)
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uint32_t app0;
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uint32_t app1;
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uint32_t app2;
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uint32_t app3;
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uint32_t app4;
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uint32_t reserved[3];
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};
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struct axidma_fdt_data {
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int id;
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};
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#endif /* !_DEV_XILINX_AXIDMA_H_ */
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