87e31f4b90
device_add_child_ordered(). 'ivars' may now be set using the device_set_ivars() function. This makes it easier for us to change how arbitrary data structures are associated with a device_t. Eventually we won't be modifying device_t to add additional pointers for ivars, softc data etc. Despite my best efforts I've probably forgotten something so let me know if this breaks anything. I've been running with this change for months and its been quite involved actually isolating all the changes from the rest of the local changes in my tree. Reviewed by: peter, dfr
388 lines
11 KiB
C
388 lines
11 KiB
C
/* $FreeBSD$ */
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/* from $NetBSD: ioasic.c,v 1.19 1998/05/27 00:18:13 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic, Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/pmap.h>
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#include <machine/rpb.h>
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#include <alpha/tc/tcreg.h>
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#include <alpha/tc/tcvar.h>
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#include <alpha/tc/tcdevs.h>
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#include <alpha/tc/ioasicreg.h>
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#include <alpha/tc/ioasicvar.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t ioasic_devclass;
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static device_t ioasic0; /* there can be only one */
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struct ioasic_softc {
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device_t sc_dv;
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vm_offset_t sc_base;
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void *sc_cookie;
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};
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#define IOASIC_SOFTC(dev) (struct ioasic_softc*) device_get_softc(dev)
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static int ioasic_probe(device_t dev);
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static int ioasic_attach(device_t dev);
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static driver_intr_t ioasic_intrnull;
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static int ioasic_print_child(device_t bus, device_t dev);
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static void ioasic_lance_dma_setup(void *v);
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int ioasic_intr __P((void *));
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caddr_t le_iomem = 0;
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static device_method_t ioasic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ioasic_probe),
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DEVMETHOD(device_attach, ioasic_attach),
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DEVMETHOD(bus_print_child, ioasic_print_child),
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{ 0, 0 }
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};
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static driver_t ioasic_driver = {
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"ioasic",
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ioasic_methods,
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sizeof(struct ioasic_softc),
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};
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#define IOASIC_DEV_LANCE 0
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#define IOASIC_DEV_SCC0 1
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#define IOASIC_DEV_SCC1 2
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#define IOASIC_DEV_ISDN 3
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#define IOASIC_DEV_BOGUS -1
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#define IOASIC_NCOOKIES 4
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#define C(x) ((void *)(u_long)x)
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struct ioasic_dev ioasic_devs[] = {
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{ "le", 0x000c0000, 0, C(IOASIC_DEV_LANCE), IOASIC_INTR_LANCE, },
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#ifdef notyet
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{ "z8530 ", 0x00100000, 0, C(IOASIC_DEV_SCC0), IOASIC_INTR_SCC_0, },
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{ "z8530 ", 0x00180000, 0, C(IOASIC_DEV_SCC1), IOASIC_INTR_SCC_1, },
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#endif
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{ "mcclock", 0x00200000, 0, C(IOASIC_DEV_BOGUS), 0, },
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#ifdef notyet
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{ "AMD79c30", 0x00240000, 0, C(IOASIC_DEV_ISDN), IOASIC_INTR_ISDN, },
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#endif
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};
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int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
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struct ioasicintr {
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void (*iai_func) __P((void *));
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void *iai_arg;
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} ioasicintrs[IOASIC_NCOOKIES];
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tc_addr_t ioasic_base; /* XXX XXX XXX */
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static int
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ioasic_probe(device_t dev)
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{
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if (ioasic0)
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return ENXIO;
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if((hwrpb->rpb_type != ST_DEC_3000_300) &&
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(hwrpb->rpb_type != ST_DEC_3000_500))
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return ENXIO;
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if(strcmp(device_get_name(dev),"ioasic")){
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return ENXIO;
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}
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ioasic0 = dev;
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if (hwrpb->rpb_type == ST_DEC_3000_300)
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device_set_desc(dev, "Turbochannel ioasic: slow mode");
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else
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device_set_desc(dev, "Turbochannel ioasic: fast mode");
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return 0;
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}
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static int
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ioasic_attach(device_t dev)
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{
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device_t child;
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struct ioasic_softc* sc = IOASIC_SOFTC(dev);
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struct tc_attach_args *ta = device_get_ivars(dev);
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device_t parent = device_get_parent(dev);
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u_long i;
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ioasic0 = dev;
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sc->sc_base = ta->ta_addr;
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sc->sc_cookie = ta->ta_cookie;
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ioasic_base = sc->sc_base;
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#ifdef DEC_3000_300
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if (hwrpb->rpb_type == ST_DEC_3000_300) {
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*(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |=
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IOASIC_CSR_FASTMODE;
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tc_mb();
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}
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#endif
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/*
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* Turn off all device interrupt bits.
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* (This does _not_ include 3000/300 TC option slot bits.
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*/
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for (i = 0; i < ioasic_ndevs; i++)
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
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~ioasic_devs[i].iad_intrbits;
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tc_mb();
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/*
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* Set up interrupt handlers.
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*/
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for (i = 0; i < IOASIC_NCOOKIES; i++) {
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ioasicintrs[i].iai_func = ioasic_intrnull;
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ioasicintrs[i].iai_arg = (void *)i;
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}
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tc_intr_establish(parent, sc->sc_cookie, 0, ioasic_intr, sc);
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#define LANCE_DMA_SIZE 128*1024
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#define LANCE_DMA_ALIGN 128*1024
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/*
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* Set up the LANCE DMA area.
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*/
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le_iomem = (caddr_t)vm_page_alloc_contig(round_page(LANCE_DMA_SIZE),
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0, 0xffffffff,LANCE_DMA_ALIGN);
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le_iomem = (caddr_t)ALPHA_PHYS_TO_K0SEG(vtophys(le_iomem));
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ioasic_lance_dma_setup((void *)le_iomem);
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/*
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* round up our children
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*/
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for (i = 0; i < ioasic_ndevs; i++) {
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ioasic_devs[i].iada_addr = sc->sc_base + ioasic_devs[i].iad_offset;
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child = device_add_child(dev, ioasic_devs[i].iad_modname, -1);
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device_set_ivars(child, &ioasic_devs[i]);
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device_probe_and_attach(child);
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}
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return 0;
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}
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static void
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ioasic_intrnull(void *val)
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{
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panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n",
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(u_long)val);
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}
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static int
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ioasic_print_child(device_t bus, device_t dev)
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{
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struct ioasic_dev *ioasic = device_get_ivars(dev);
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int retval = 0;
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retval += bus_print_child_header(bus, dev);
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retval += printf(" on %s offset 0x%x\n", device_get_nameunit(bus),
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ioasic->iad_offset);
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return (retval);
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}
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char *
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ioasic_lance_ether_address()
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{
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return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base);
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}
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static void
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ioasic_lance_dma_setup(void *v)
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{
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volatile u_int32_t *ldp;
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tc_addr_t tca;
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tca = (tc_addr_t)v;
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tca &= 0xffffffff;
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ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base);
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*ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f);
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tc_wmb();
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*(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |=
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IOASIC_CSR_DMAEN_LANCE;
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tc_mb();
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}
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void
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ioasic_intr_establish(ioa, cookie, level, func, arg)
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device_t ioa;
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void *cookie, *arg;
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tc_intrlevel_t level;
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void (*func) __P((void *));
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{
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u_long dev, i;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func != ioasic_intrnull)
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panic("ioasic_intr_establish: cookie %ld twice", dev);
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ioasicintrs[dev].iai_func = func;
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ioasicintrs[dev].iai_arg = arg;
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_establish: invalid cookie.");
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |=
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ioasic_devs[i].iad_intrbits;
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tc_mb();
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}
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void
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ioasic_intr_disestablish(ioa, cookie)
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device_t ioa;
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void *cookie;
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{
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u_long dev, i;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func == ioasic_intrnull)
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panic("ioasic_intr_disestablish: cookie %ld missing intr", dev);
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_disestablish: invalid cookie.");
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
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~ioasic_devs[i].iad_intrbits;
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tc_mb();
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ioasicintrs[dev].iai_func = ioasic_intrnull;
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ioasicintrs[dev].iai_arg = (void *)dev;
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}
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/*
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* asic_intr --
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* ASIC interrupt handler.
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*/
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int
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ioasic_intr(val)
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void *val;
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{
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register struct ioasic_softc *sc = val;
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register int ifound;
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int gifound;
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u_int32_t sir;
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volatile u_int32_t *sirp;
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sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base);
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gifound = 0;
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do {
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ifound = 0;
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tc_syncbus();
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sir = *sirp;
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/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
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#define CHECKINTR(slot, bits) \
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if (sir & bits) { \
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ifound = 1; \
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(*ioasicintrs[slot].iai_func) \
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(ioasicintrs[slot].iai_arg); \
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}
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CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0);
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CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1);
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CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE);
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CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN);
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gifound |= ifound;
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} while (ifound);
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return (gifound);
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}
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DRIVER_MODULE(ioasic, tc, ioasic_driver, ioasic_devclass, 0, 0);
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