3dc9275fe3
library:
o) Increase inline unit / large function growth limits for MIPS to accommodate
the needs of the Simple Executive, which uses a shocking amount of inlining.
o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and
the Octeon SoC.
o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific
board numbers, specifically to support the MR320.
o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd,
which improperly uses an evaluation board's board number and breaks board
detection at runtime. This board is sold by Portwell as the CAM-0100.
o) Add support for the RTC available on some Octeon boards.
o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO
ports can not work unless building for n64.
o) Clean up the CompactFlash driver to use Simple Executive macros and
structures where possible (it would be advisable to use the Simple Executive
API to set the PIO mode, too, but that is not done presently.) Also use
structures from FreeBSD's ATA layer rather than structures copied from
Linux.
o) Print available Octeon SoC features on boot.
o) Add support for the Octeon timecounter.
o) Use the Simple Executive's routines rather than local copies for doing reads
and writes to 64-bit addresses and use its macros for various device
addresses rather than using local copies.
o) Rename octeon_board_real to octeon_is_simulation to reduce differences with
Cavium-provided code originally written for Linux. Also make it use the
same simplified test that the Simple Executive and Linux both use rather
than our complex one.
o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus
to use normal interrupt allocation and setup routines.
o) Use the Simple Executive's bootmem facility to allocate physical memory for
the kernel, rather than assuming we know which addresses we can steal.
NB: This may reduce the amount of RAM the kernel reports you as having if
you are leaving large temporary allocations made by U-Boot allocated
when starting FreeBSD.
o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes
Ethernet interface naming from rgmxN to octeN. The new driver has vast
improvements over the old one, both in performance and functionality, but
does still have some features which have not been ported entirely and there
may be unimplemented code that can be hit in everyday use. I will make
every effort to correct those as they are reported.
o) Support loading the kernel on non-contiguous cores.
o) Add very conservative support for harvesting randomness from the Octeon
random number device.
o) Turn SMP on by default.
o) Clean up the style of the Octeon kernel configurations a little and make
them compile with -march=octeon.
o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple
Executive.
o) Modify the Simple Executive to build on FreeBSD and to build without
executive-config.h or cvmx-config.h. In the future we may want to
revert part of these changes and supply executive-config.h and
cvmx-config.h and access to the options contained in those files via
kernel configuration files.
o) Modify the Simple Executive USB routines to support getting and setting
of the USB PID.
607 lines
22 KiB
C
607 lines
22 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Support functions for managing command queues used for
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* various hardware blocks.
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*
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* The common command queue infrastructure abstracts out the
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* software necessary for adding to Octeon's chained queue
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* structures. These structures are used for commands to the
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* PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
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* hardware unit takes commands and CSRs of different types,
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* they all use basic linked command buffers to store the
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* pending request. In general, users of the CVMX API don't
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* call cvmx-cmd-queue functions directly. Instead the hardware
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* unit specific wrapper should be used. The wrappers perform
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* unit specific validation and CSR writes to submit the
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* commands.
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*
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* Even though most software will never directly interact with
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* cvmx-cmd-queue, knowledge of its internal working can help
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* in diagnosing performance problems and help with debugging.
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*
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* Command queue pointers are stored in a global named block
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* called "cvmx_cmd_queues". Except for the PKO queues, each
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* hardware queue is stored in its own cache line to reduce SMP
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* contention on spin locks. The PKO queues are stored such that
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* every 16th queue is next to each other in memory. This scheme
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* allows for queues being in separate cache lines when there
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* are low number of queues per port. With 16 queues per port,
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* the first queue for each port is in the same cache area. The
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* second queues for each port are in another area, etc. This
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* allows software to implement very efficient lockless PKO with
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* 16 queues per port using a minimum of cache lines per core.
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* All queues for a given core will be isolated in the same
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* cache area.
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*
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* In addition to the memory pointer layout, cvmx-cmd-queue
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* provides an optimized fair ll/sc locking mechanism for the
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* queues. The lock uses a "ticket / now serving" model to
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* maintain fair order on contended locks. In addition, it uses
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* predicted locking time to limit cache contention. When a core
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* know it must wait in line for a lock, it spins on the
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* internal cycle counter to completely eliminate any causes of
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* bus traffic.
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*
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* <hr> $Revision: 42150 $ <hr>
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*/
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#ifndef __CVMX_CMD_QUEUE_H__
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#define __CVMX_CMD_QUEUE_H__
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#ifndef CVMX_DONT_INCLUDE_CONFIG
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#include "executive-config.h"
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#include "cvmx-config.h"
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#endif
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#include "cvmx-fpa.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* By default we disable the max depth support. Most programs
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* don't use it and it slows down the command queue processing
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* significantly.
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*/
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#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
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#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
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#endif
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/**
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* Enumeration representing all hardware blocks that use command
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* queues. Each hardware block has up to 65536 sub identifiers for
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* multiple command queues. Not all chips support all hardware
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* units.
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*/
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typedef enum
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{
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CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
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#define CVMX_CMD_QUEUE_PKO(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
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CVMX_CMD_QUEUE_ZIP = 0x10000,
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CVMX_CMD_QUEUE_DFA = 0x20000,
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CVMX_CMD_QUEUE_RAID = 0x30000,
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CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
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#define CVMX_CMD_QUEUE_DMA(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
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CVMX_CMD_QUEUE_END = 0x50000,
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} cvmx_cmd_queue_id_t;
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/**
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* Command write operations can fail if the comamnd queue needs
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* a new buffer and the associated FPA pool is empty. It can also
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* fail if the number of queued command words reaches the maximum
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* set at initialization.
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*/
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typedef enum
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{
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CVMX_CMD_QUEUE_SUCCESS = 0,
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CVMX_CMD_QUEUE_NO_MEMORY = -1,
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CVMX_CMD_QUEUE_FULL = -2,
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CVMX_CMD_QUEUE_INVALID_PARAM = -3,
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CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
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} cvmx_cmd_queue_result_t;
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typedef struct
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{
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uint8_t now_serving; /**< You have lock when this is your ticket */
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uint64_t unused1 : 24;
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uint32_t max_depth; /**< Maximum outstanding command words */
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uint64_t fpa_pool : 3; /**< FPA pool buffers come from */
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uint64_t base_ptr_div128: 29; /**< Top of command buffer pointer shifted 7 */
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uint64_t unused2 : 6;
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uint64_t pool_size_m1 : 13; /**< FPA buffer size in 64bit words minus 1 */
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uint64_t index : 13; /**< Number of comamnds already used in buffer */
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} __cvmx_cmd_queue_state_t;
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/**
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* This structure contains the global state of all comamnd queues.
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* It is stored in a bootmem named block and shared by all
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* applications running on Octeon. Tickets are stored in a differnet
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* cahce line that queue information to reduce the contention on the
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* ll/sc used to get a ticket. If this is not the case, the update
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* of queue state causes the ll/sc to fail quite often.
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*/
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typedef struct
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{
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uint64_t ticket[(CVMX_CMD_QUEUE_END>>16) * 256];
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__cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END>>16) * 256];
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} __cvmx_cmd_queue_all_state_t;
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extern CVMX_SHARED __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
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/**
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* Initialize a command queue for use. The initial FPA buffer is
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* allocated and the hardware unit is configured to point to the
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* new command queue.
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*
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* @param queue_id Hardware command queue to initialize.
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* @param max_depth Maximum outstanding commands that can be queued.
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* @param fpa_pool FPA pool the command queues should come from.
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* @param pool_size Size of each buffer in the FPA pool (bytes)
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, int max_depth, int fpa_pool, int pool_size);
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/**
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* Shutdown a queue a free it's command buffers to the FPA. The
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* hardware connected to the queue must be stopped before this
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* function is called.
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*
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* @param queue_id Queue to shutdown
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
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/**
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* Return the number of command words pending in the queue. This
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* function may be relatively slow for some hardware units.
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*
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* @param queue_id Hardware command queue to query
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*
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* @return Number of outstanding commands
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*/
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int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
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/**
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* Return the command buffer to be written to. The purpose of this
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* function is to allow CVMX routine access t othe low level buffer
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* for initial hardware setup. User applications should not call this
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* function directly.
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*
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* @param queue_id Command queue to query
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*
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* @return Command buffer or NULL on failure
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*/
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void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
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/**
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* @INTERNAL
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* Get the index into the state arrays for the supplied queue id.
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*
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* @param queue_id Queue ID to get an index for
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*
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* @return Index into the state arrays
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*/
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static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
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{
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/* Warning: This code currently only works with devices that have 256 queues
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or less. Devices with more than 16 queues are layed out in memory to allow
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cores quick access to every 16th queue. This reduces cache thrashing
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when you are running 16 queues per port to support lockless operation */
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int unit = queue_id>>16;
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int q = (queue_id >> 4) & 0xf;
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int core = queue_id & 0xf;
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return unit*256 + core*16 + q;
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}
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/**
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* @INTERNAL
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* Lock the supplied queue so nobody else is updating it at the same
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* time as us.
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*
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* @param queue_id Queue ID to lock
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* @param qptr Pointer to the queue's global state
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*/
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static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, __cvmx_cmd_queue_state_t *qptr)
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{
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int tmp;
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int my_ticket;
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CVMX_PREFETCH(qptr, 0);
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asm volatile (
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".set push\n"
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".set noreorder\n"
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"1:\n"
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"ll %[my_ticket], %[ticket_ptr]\n" /* Atomic add one to ticket_ptr */
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"li %[ticket], 1\n" /* and store the original value */
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"baddu %[ticket], %[my_ticket]\n" /* in my_ticket */
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"sc %[ticket], %[ticket_ptr]\n"
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"beqz %[ticket], 1b\n"
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" nop\n"
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"lbu %[ticket], %[now_serving]\n" /* Load the current now_serving ticket */
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"2:\n"
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"beq %[ticket], %[my_ticket], 4f\n" /* Jump out if now_serving == my_ticket */
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" subu %[ticket], %[my_ticket], %[ticket]\n" /* Find out how many tickets are in front of me */
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"subu %[ticket], 1\n" /* Use tickets in front of me minus one to delay */
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"cins %[ticket], %[ticket], 5, 7\n" /* Delay will be ((tickets in front)-1)*32 loops */
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"3:\n"
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"bnez %[ticket], 3b\n" /* Loop here until our ticket might be up */
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" subu %[ticket], 1\n"
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"b 2b\n" /* Jump back up to check out ticket again */
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" lbu %[ticket], %[now_serving]\n" /* Load the current now_serving ticket */
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"4:\n"
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".set pop\n"
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: [ticket_ptr] "=m" (__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
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[now_serving] "=m" (qptr->now_serving),
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[ticket] "=r" (tmp),
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[my_ticket] "=r" (my_ticket)
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);
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}
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/**
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* @INTERNAL
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* Unlock the queue, flushing all writes.
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*
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* @param qptr Queue to unlock
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*/
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static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
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{
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qptr->now_serving++;
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CVMX_SYNCWS;
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}
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/**
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* @INTERNAL
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* Get the queue state structure for the given queue id
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*
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* @param queue_id Queue id to get
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*
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* @return Queue structure or NULL on failure
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*/
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static inline __cvmx_cmd_queue_state_t *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
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{
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if (CVMX_ENABLE_PARAMETER_CHECKING)
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{
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if (cvmx_unlikely(queue_id >= CVMX_CMD_QUEUE_END))
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return NULL;
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if (cvmx_unlikely((queue_id & 0xffff) >= 256))
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return NULL;
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}
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return &__cvmx_cmd_queue_state_ptr->state[__cvmx_cmd_queue_get_index(queue_id)];
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}
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/**
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* Write an arbitrary number of command words to a command queue.
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* This is a generic function; the fixed number of comamnd word
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* functions yield higher performance.
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*
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* @param queue_id Hardware command queue to write to
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* @param use_locking
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* Use internal locking to ensure exclusive access for queue
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* updates. If you don't use this locking you must ensure
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* exclusivity some other way. Locking is strongly recommended.
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* @param cmd_count Number of command words to write
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* @param cmds Array of comamnds to write
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t queue_id, int use_locking, int cmd_count, uint64_t *cmds)
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{
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__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
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if (CVMX_ENABLE_PARAMETER_CHECKING)
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{
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if (cvmx_unlikely(qptr == NULL))
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return CVMX_CMD_QUEUE_INVALID_PARAM;
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if (cvmx_unlikely((cmd_count < 1) || (cmd_count > 32)))
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return CVMX_CMD_QUEUE_INVALID_PARAM;
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if (cvmx_unlikely(cmds == NULL))
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return CVMX_CMD_QUEUE_INVALID_PARAM;
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}
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/* Make sure nobody else is updating the same queue */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_lock(queue_id, qptr);
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/* If a max queue length was specified then make sure we don't
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exceed it. If any part of the command would be below the limit
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we allow it */
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if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
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{
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if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
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{
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_unlock(qptr);
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return CVMX_CMD_QUEUE_FULL;
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}
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}
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/* Normally there is plenty of room in the current buffer for the command */
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if (cvmx_likely(qptr->index + cmd_count < qptr->pool_size_m1))
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{
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uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
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ptr += qptr->index;
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qptr->index += cmd_count;
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while (cmd_count--)
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*ptr++ = *cmds++;
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}
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else
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{
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uint64_t *ptr;
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int count;
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/* We need a new comamnd buffer. Fail if there isn't one available */
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uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
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if (cvmx_unlikely(new_buffer == NULL))
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{
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_unlock(qptr);
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return CVMX_CMD_QUEUE_NO_MEMORY;
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}
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ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
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/* Figure out how many command words will fit in this buffer. One
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location will be needed for the next buffer pointer */
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count = qptr->pool_size_m1 - qptr->index;
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ptr += qptr->index;
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cmd_count-=count;
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while (count--)
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*ptr++ = *cmds++;
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*ptr = cvmx_ptr_to_phys(new_buffer);
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/* The current buffer is full and has a link to the next buffer. Time
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to write the rest of the commands into the new buffer */
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qptr->base_ptr_div128 = *ptr >> 7;
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qptr->index = cmd_count;
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ptr = new_buffer;
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|
while (cmd_count--)
|
|
*ptr++ = *cmds++;
|
|
}
|
|
|
|
/* All updates are complete. Release the lock and return */
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_SUCCESS;
|
|
}
|
|
|
|
|
|
/**
|
|
* Simple function to write two command words to a command
|
|
* queue.
|
|
*
|
|
* @param queue_id Hardware command queue to write to
|
|
* @param use_locking
|
|
* Use internal locking to ensure exclusive access for queue
|
|
* updates. If you don't use this locking you must ensure
|
|
* exclusivity some other way. Locking is strongly recommended.
|
|
* @param cmd1 Command
|
|
* @param cmd2 Command
|
|
*
|
|
* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
|
|
*/
|
|
static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2)
|
|
{
|
|
__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
|
|
|
|
if (CVMX_ENABLE_PARAMETER_CHECKING)
|
|
{
|
|
if (cvmx_unlikely(qptr == NULL))
|
|
return CVMX_CMD_QUEUE_INVALID_PARAM;
|
|
}
|
|
|
|
/* Make sure nobody else is updating the same queue */
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_lock(queue_id, qptr);
|
|
|
|
/* If a max queue length was specified then make sure we don't
|
|
exceed it. If any part of the command would be below the limit
|
|
we allow it */
|
|
if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
|
|
{
|
|
if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
|
|
{
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_FULL;
|
|
}
|
|
}
|
|
|
|
/* Normally there is plenty of room in the current buffer for the command */
|
|
if (cvmx_likely(qptr->index + 2 < qptr->pool_size_m1))
|
|
{
|
|
uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
|
|
ptr += qptr->index;
|
|
qptr->index += 2;
|
|
ptr[0] = cmd1;
|
|
ptr[1] = cmd2;
|
|
}
|
|
else
|
|
{
|
|
uint64_t *ptr;
|
|
/* Figure out how many command words will fit in this buffer. One
|
|
location will be needed for the next buffer pointer */
|
|
int count = qptr->pool_size_m1 - qptr->index;
|
|
/* We need a new comamnd buffer. Fail if there isn't one available */
|
|
uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
|
|
if (cvmx_unlikely(new_buffer == NULL))
|
|
{
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_NO_MEMORY;
|
|
}
|
|
count--;
|
|
ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
|
|
ptr += qptr->index;
|
|
*ptr++ = cmd1;
|
|
if (cvmx_likely(count))
|
|
*ptr++ = cmd2;
|
|
*ptr = cvmx_ptr_to_phys(new_buffer);
|
|
/* The current buffer is full and has a link to the next buffer. Time
|
|
to write the rest of the commands into the new buffer */
|
|
qptr->base_ptr_div128 = *ptr >> 7;
|
|
qptr->index = 0;
|
|
if (cvmx_unlikely(count == 0))
|
|
{
|
|
qptr->index = 1;
|
|
new_buffer[0] = cmd2;
|
|
}
|
|
}
|
|
|
|
/* All updates are complete. Release the lock and return */
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_SUCCESS;
|
|
}
|
|
|
|
|
|
/**
|
|
* Simple function to write three command words to a command
|
|
* queue.
|
|
*
|
|
* @param queue_id Hardware command queue to write to
|
|
* @param use_locking
|
|
* Use internal locking to ensure exclusive access for queue
|
|
* updates. If you don't use this locking you must ensure
|
|
* exclusivity some other way. Locking is strongly recommended.
|
|
* @param cmd1 Command
|
|
* @param cmd2 Command
|
|
* @param cmd3 Command
|
|
*
|
|
* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
|
|
*/
|
|
static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t queue_id, int use_locking, uint64_t cmd1, uint64_t cmd2, uint64_t cmd3)
|
|
{
|
|
__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
|
|
|
|
if (CVMX_ENABLE_PARAMETER_CHECKING)
|
|
{
|
|
if (cvmx_unlikely(qptr == NULL))
|
|
return CVMX_CMD_QUEUE_INVALID_PARAM;
|
|
}
|
|
|
|
/* Make sure nobody else is updating the same queue */
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_lock(queue_id, qptr);
|
|
|
|
/* If a max queue length was specified then make sure we don't
|
|
exceed it. If any part of the command would be below the limit
|
|
we allow it */
|
|
if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && cvmx_unlikely(qptr->max_depth))
|
|
{
|
|
if (cvmx_unlikely(cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth))
|
|
{
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_FULL;
|
|
}
|
|
}
|
|
|
|
/* Normally there is plenty of room in the current buffer for the command */
|
|
if (cvmx_likely(qptr->index + 3 < qptr->pool_size_m1))
|
|
{
|
|
uint64_t *ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
|
|
ptr += qptr->index;
|
|
qptr->index += 3;
|
|
ptr[0] = cmd1;
|
|
ptr[1] = cmd2;
|
|
ptr[2] = cmd3;
|
|
}
|
|
else
|
|
{
|
|
uint64_t *ptr;
|
|
/* Figure out how many command words will fit in this buffer. One
|
|
location will be needed for the next buffer pointer */
|
|
int count = qptr->pool_size_m1 - qptr->index;
|
|
/* We need a new comamnd buffer. Fail if there isn't one available */
|
|
uint64_t *new_buffer = (uint64_t *)cvmx_fpa_alloc(qptr->fpa_pool);
|
|
if (cvmx_unlikely(new_buffer == NULL))
|
|
{
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_NO_MEMORY;
|
|
}
|
|
count--;
|
|
ptr = (uint64_t *)cvmx_phys_to_ptr((uint64_t)qptr->base_ptr_div128<<7);
|
|
ptr += qptr->index;
|
|
*ptr++ = cmd1;
|
|
if (count)
|
|
{
|
|
*ptr++ = cmd2;
|
|
if (count > 1)
|
|
*ptr++ = cmd3;
|
|
}
|
|
*ptr = cvmx_ptr_to_phys(new_buffer);
|
|
/* The current buffer is full and has a link to the next buffer. Time
|
|
to write the rest of the commands into the new buffer */
|
|
qptr->base_ptr_div128 = *ptr >> 7;
|
|
qptr->index = 0;
|
|
ptr = new_buffer;
|
|
if (count == 0)
|
|
{
|
|
*ptr++ = cmd2;
|
|
qptr->index++;
|
|
}
|
|
if (count < 2)
|
|
{
|
|
*ptr++ = cmd3;
|
|
qptr->index++;
|
|
}
|
|
}
|
|
|
|
/* All updates are complete. Release the lock and return */
|
|
if (cvmx_likely(use_locking))
|
|
__cvmx_cmd_queue_unlock(qptr);
|
|
return CVMX_CMD_QUEUE_SUCCESS;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __CVMX_CMD_QUEUE_H__ */
|