freebsd-skq/sys/contrib/octeon-sdk/cvmx-twsi-raw.c
jmallett 4948f4b8d5 Import the Cavium Simple Executive from the Cavium Octeon SDK. The Simple
Executive is a library that can be used by standalone applications and kernels
to abstract access to Octeon SoC and board-specific hardware and facilities.
The FreeBSD port to Octeon will be updated to use this where possible.
2010-07-20 07:19:43 +00:00

465 lines
20 KiB
C

/***********************license start***************
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* OCTEON SDK License Type 4:
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* This file is part of the OCTEON SDK
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* Copyright (c) 2007 Cavium Networks
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* Contact Cavium Networks for more information
***********************license end**************************************/
/*
* This code is an example of using twsi core in raw mode, bypasing High
* Level Controller (HLC). It is recommended to use HLC if only possible as
* it is more efficient and robust mechanism.
* The example code shows use of twsi for generating long (more that 8 bytes HLC limit)
* read - write transactions using 7-bit addressing. Different types of
* transactions can be generated if needed. Make sure that commands written to twsi core
* follow core state transitions outlinged in OCTEON documentation. The core state is
* reported in stat register after the command colpletion. In each state core will accept
* only the allowed commands.
*/
#include <stdio.h>
#include <cvmx.h>
#include <cvmx-csr-typedefs.h>
#include "cvmx-twsi-raw.h"
/*
* uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
* twsi core register read
* twsi_id - twsi core index
* reg 0 - 8-bit register
* returns 8-bit register contetn
*/
uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
{
cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
sw_twsi_val.u64 = 0;
sw_twsi_val.s.v = 1;
sw_twsi_val.s.op = 6;
sw_twsi_val.s.eop_ia = reg;
sw_twsi_val.s.r = 1;
cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
;
return sw_twsi_val.s.d ;
}
/*
* uint8_t cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
*
* twsi core register write
* twsi_id - twsi core index
* reg 0 - 8-bit register
* data - data to write
* returns 0;
*/
int cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
{
cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
sw_twsi_val.u64 = 0;
sw_twsi_val.s.v = 1;
sw_twsi_val.s.op = 6;
sw_twsi_val.s.eop_ia = reg;
sw_twsi_val.s.d = data;
cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
;
return 0;
}
/*
* cvmx_twsi_wait_iflg(int twsi_id)
* cvmx_twsi_wait_stop(int twsi_id)
*
* Helper functions.
* Busy wait for interrupt flag or stop bit on control register. This implementation is for OS-less
* application. With OS services available it could be implemented with semaphore
* block and interrupt wake up.
* TWSI_WAIT for loop must be defined large enough to allow on-wire transaction to finish - that is
* about 10 twsi clocks
*/
#define TWSI_WAIT 10000000
static inline int cvmx_twsi_wait_iflg(int twsi_id)
{
octeon_twsi_ctl_t ctl_reg;
int wait = TWSI_WAIT;
do{
ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
} while((ctl_reg.s.iflg ==0) && (wait-- >0));
if(wait == 0) return -1;
return 0;
}
static inline int cvmx_twsi_wait_stop(int twsi_id)
{
octeon_twsi_ctl_t ctl_reg;
int wait = TWSI_WAIT;
do{
ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
} while((ctl_reg.s.stp ==1) && (wait-- >0));
if(wait == 0) return -1;
return 0;
}
/*
* uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
* uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
*
* helper functions - read or write byte to data reg and reads the TWSI core status
*/
static uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
{
octeon_twsi_ctl_t ctl_reg;
octeon_twsi_data_t data;
octeon_twsi_stat_t stat;
/* clear interrupt flag, set aak for requested ACK signal level */
ctl_reg.u8 =0;
ctl_reg.s.aak = (ack==0) ?0:1;
ctl_reg.s.enab =1;
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
/* wait for twsi_ctl[iflg] to be set */
if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
/* read the byte */
data.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_DATA_REG);
*byte = data.s.data;
error:
/* read the status */
stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
return stat.s.stat;
}
static uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
{
octeon_twsi_ctl_t ctl_reg;
octeon_twsi_data_t data;
octeon_twsi_stat_t stat;
/* tx data byte - write to twsi_data reg, then clear twsi_ctl[iflg] */
data.s.data = byte;
cvmx_twsix_write_ctr(twsi_id, TWSI_DATA_REG, data.u8);
ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
ctl_reg.s.iflg =0;
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
/* wait for twsi_ctl[iflg] to be set */
if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
error:
/* read the status */
stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
return stat.s.stat;
}
/*
* int octeon_i2c_xfer_msg_raw(struct i2c_msg *msg)
*
* Send (read or write) a message with 7-bit address device over direct control of
* TWSI core, bypassind HLC. Will try to finish the transaction on failure, so core state
* expected to be idle with HLC enabled on exit.
*
* dev - TWSI controller index (0 for cores with single controler)
* msg - message to transfer
* returns 0 on success, TWSI core state on error. Will try to finish the transaction on failure, so core state expected to be idle
*/
int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg)
{
int i =0;
octeon_twsi_ctl_t ctl_reg;
octeon_twsi_addr_t addr;
octeon_twsi_stat_t stat;
int is_read = msg->flags & I2C_M_RD;
int ret =0;
/* check the core state, quit if not idle */
stat.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
if(stat.s.stat != TWSI_IDLE) {
msg->len =0; return stat.s.stat;
}
/* first send start - set twsi_ctl[sta] to 1 */
ctl_reg.u8 =0;
ctl_reg.s.enab =1;
ctl_reg.s.sta =1;
ctl_reg.s.iflg =0;
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
/* wait for twsi_ctl[iflg] to be set */
if(cvmx_twsi_wait_iflg(twsi_id)) goto stop;
/* Write 7-bit addr to twsi_data; set read bit */
addr.s.slave_addr7 = msg->addr;
if(is_read) addr.s.r =1;
else addr.s.r =0;
stat.s.stat =octeon_twsi_write_byte(twsi_id, addr.u8);
/* Data read loop */
if( is_read) {
/* any status but ACK_RXED means failure - we try to send stop and go idle */
if(!(stat.s.stat == TWSI_ADDR_R_TX_ACK_RXED)) {
ret = stat.s.stat;
msg->len =0;
goto stop;
}
/* We read data from the buffer and send ACK back.
The last byte we read with negative ACK */
for(i =0; i<msg->len-1; i++)
{
stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 1);
if(stat.s.stat != TWSI_DATA_RX_ACK_TXED)
goto stop;
}
/* last read we send negACK */
stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 0);
if(stat.s.stat != TWSI_DATA_RX_NACK_TXED)
return stat.s.stat;
} /* read loop */
/* Data write loop */
else {
/* any status but ACK_RXED means failure - we try to send stop and go idle */
if(stat.s.stat != TWSI_ADDR_W_TX_ACK_RXED) {
ret = stat.s.stat;
msg->len =0;
goto stop;
}
/* We write data to the buffer and check for ACK. */
for(i =0; i<msg->len; i++)
{
stat.s.stat =octeon_twsi_write_byte(twsi_id, msg->buf[i]);
if(stat.s.stat == TWSI_DATA_TX_NACK_RXED) {
/* Negative ACK means slave can not RX more */
msg->len =i-1;
goto stop;
}
else if(stat.s.stat != TWSI_DATA_TX_ACK_RXED) {
/* lost arbitration? try to send stop and go idle. This current byte likely was not written */
msg->len = (i-2) >0? (i-2):0;
goto stop;
}
}
} /* write loop */
stop:
ctl_reg.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
ctl_reg.s.stp =1;
ctl_reg.s.iflg =0;
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
/* wait for twsi_ctl[stp] to clear */
cvmx_twsi_wait_stop(twsi_id);
#if 0
stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
if(stat.s.stat == TWSI_IDLE)
#endif
/* Leave TWSI core with HLC eabled */
{
ctl_reg.u8 =0;
ctl_reg.s.ce =1;
ctl_reg.s.enab =1;
ctl_reg.s.aak =1;
cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
}
return ret;
}