Justin T. Gibbs 499c4ce9f6 Clear the DFCNTRL register after every busfree.
When setting the HCNT registers, do so in ascending order.

When performing tagged queueing in non-paging mode, also check the
disconnected bit in the SCB as extra sanity during a reconection.

Make the labels in the DMA routine more sane.

When doing a DMA, if we see the DMADONE condition come true, we can
simply turn of the DMA enable bits in DFCNTRL without testing the FIFO
state as HDONE is true when DMADONE is true and this emplies the FIFO is
empty.

These changes clear up the data overrun error messages and seem to prevent
the "timed out in data-in phase" problems.
1997-02-11 17:07:54 +00:00
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1997-02-11 09:29:48 +00:00
1997-01-23 16:17:09 +00:00
1996-09-10 08:32:01 +00:00