faed057a37
avoid lost timer interrupts. Previous optimization attempt doing it only for intervals less then 5000 ticks (~300us) reported to be unreliable by some people. Probably because of some heavy SMI code on their boards. Introduce additional safety interval of 128 counter ticks (~9us) between programmed comparator and counter values to cover different cases of delayed write found on some chipsets. Approved by: re (kib)
68 lines
2.9 KiB
C
68 lines
2.9 KiB
C
/*-
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* Copyright (c) 2005 Poul-Henning Kamp
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __ACPI_HPET_H__
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#define __ACPI_HPET_H__
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#define HPET_MEM_WIDTH 0x400 /* Expected memory region size */
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/* General registers */
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#define HPET_CAPABILITIES 0x0 /* General capabilities and ID */
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#define HPET_CAP_VENDOR_ID 0xffff0000
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#define HPET_CAP_LEG_RT 0x00008000
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#define HPET_CAP_COUNT_SIZE 0x00002000 /* 1 = 64-bit, 0 = 32-bit */
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#define HPET_CAP_NUM_TIM 0x00001f00
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#define HPET_CAP_REV_ID 0x000000ff
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#define HPET_PERIOD 0x4 /* Period (1/hz) of timer */
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#define HPET_CONFIG 0x10 /* General configuration register */
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#define HPET_CNF_LEG_RT 0x00000002
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#define HPET_CNF_ENABLE 0x00000001
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#define HPET_ISR 0x20 /* General interrupt status register */
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#define HPET_MAIN_COUNTER 0xf0 /* Main counter register */
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/* Timer registers */
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#define HPET_TIMER_CAP_CNF(x) ((x) * 0x20 + 0x100)
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#define HPET_TCAP_INT_ROUTE 0xffffffff00000000
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#define HPET_TCAP_FSB_INT_DEL 0x00008000
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#define HPET_TCNF_FSB_EN 0x00004000
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#define HPET_TCNF_INT_ROUTE 0x00003e00
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#define HPET_TCNF_32MODE 0x00000100
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#define HPET_TCNF_VAL_SET 0x00000040
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#define HPET_TCAP_SIZE 0x00000020 /* 1 = 64-bit, 0 = 32-bit */
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#define HPET_TCAP_PER_INT 0x00000010 /* Supports periodic interrupts */
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#define HPET_TCNF_TYPE 0x00000008 /* 1 = periodic, 0 = one-shot */
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#define HPET_TCNF_INT_ENB 0x00000004
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#define HPET_TCNF_INT_TYPE 0x00000002 /* 1 = level triggered, 0 = edge */
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#define HPET_TIMER_COMPARATOR(x) ((x) * 0x20 + 0x108)
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#define HPET_TIMER_FSB_VAL(x) ((x) * 0x20 + 0x110)
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#define HPET_TIMER_FSB_ADDR(x) ((x) * 0x20 + 0x114)
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#define HPET_MIN_CYCLES 128 /* Period considered reliable. */
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#endif /* !__ACPI_HPET_H__ */
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