49bbfbc525
link state and detach request. While I'm here make sure established link is IFM_10_T or IFM_100_TX as bfe(4) just supports 10/100Mbps media. Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com Ulrich Spoerlein uspoerlein at gmail dot com
1810 lines
44 KiB
C
1810 lines
44 KiB
C
/*-
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* Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
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* and Duncan Barclay<dmlb@dmlb.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <dev/bfe/if_bfereg.h>
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MODULE_DEPEND(bfe, pci, 1, 1, 1);
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MODULE_DEPEND(bfe, ether, 1, 1, 1);
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MODULE_DEPEND(bfe, miibus, 1, 1, 1);
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/* "device miibus" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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#define BFE_DEVDESC_MAX 64 /* Maximum device description length */
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static struct bfe_type bfe_devs[] = {
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
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"Broadcom BCM4401 Fast Ethernet" },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
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"Broadcom BCM4401-B0 Fast Ethernet" },
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{ 0, 0, NULL }
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};
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static int bfe_probe (device_t);
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static int bfe_attach (device_t);
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static int bfe_detach (device_t);
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static int bfe_suspend (device_t);
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static int bfe_resume (device_t);
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static void bfe_release_resources (struct bfe_softc *);
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static void bfe_intr (void *);
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static int bfe_encap (struct bfe_softc *, struct mbuf **);
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static void bfe_start (struct ifnet *);
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static void bfe_start_locked (struct ifnet *);
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static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
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static void bfe_init (void *);
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static void bfe_init_locked (void *);
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static void bfe_stop (struct bfe_softc *);
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static void bfe_watchdog (struct bfe_softc *);
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static int bfe_shutdown (device_t);
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static void bfe_tick (void *);
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static void bfe_txeof (struct bfe_softc *);
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static void bfe_rxeof (struct bfe_softc *);
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static void bfe_set_rx_mode (struct bfe_softc *);
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static int bfe_list_rx_init (struct bfe_softc *);
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static void bfe_list_tx_init (struct bfe_softc *);
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static void bfe_discard_buf (struct bfe_softc *, int);
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static int bfe_list_newbuf (struct bfe_softc *, int);
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static void bfe_rx_ring_free (struct bfe_softc *);
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static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
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static int bfe_ifmedia_upd (struct ifnet *);
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static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
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static int bfe_miibus_readreg (device_t, int, int);
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static int bfe_miibus_writereg (device_t, int, int, int);
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static void bfe_miibus_statchg (device_t);
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static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
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u_long, const int);
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static void bfe_get_config (struct bfe_softc *sc);
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static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
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static void bfe_stats_update (struct bfe_softc *);
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static void bfe_clear_stats (struct bfe_softc *);
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static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
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static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
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static int bfe_resetphy (struct bfe_softc *);
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static int bfe_setupphy (struct bfe_softc *);
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static void bfe_chip_reset (struct bfe_softc *);
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static void bfe_chip_halt (struct bfe_softc *);
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static void bfe_core_reset (struct bfe_softc *);
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static void bfe_core_disable (struct bfe_softc *);
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static int bfe_dma_alloc (struct bfe_softc *);
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static void bfe_dma_free (struct bfe_softc *sc);
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static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
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static void bfe_cam_write (struct bfe_softc *, u_char *, int);
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static device_method_t bfe_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, bfe_probe),
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DEVMETHOD(device_attach, bfe_attach),
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DEVMETHOD(device_detach, bfe_detach),
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DEVMETHOD(device_shutdown, bfe_shutdown),
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DEVMETHOD(device_suspend, bfe_suspend),
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DEVMETHOD(device_resume, bfe_resume),
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/* bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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/* MII interface */
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DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
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DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
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DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
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{ 0, 0 }
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};
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static driver_t bfe_driver = {
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"bfe",
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bfe_methods,
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sizeof(struct bfe_softc)
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};
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static devclass_t bfe_devclass;
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DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
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DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
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/*
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* Probe for a Broadcom 4401 chip.
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*/
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static int
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bfe_probe(device_t dev)
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{
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struct bfe_type *t;
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t = bfe_devs;
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while (t->bfe_name != NULL) {
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if (pci_get_vendor(dev) == t->bfe_vid &&
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pci_get_device(dev) == t->bfe_did) {
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device_set_desc(dev, t->bfe_name);
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return (BUS_PROBE_DEFAULT);
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}
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t++;
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}
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return (ENXIO);
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}
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struct bfe_dmamap_arg {
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bus_addr_t bfe_busaddr;
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};
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static int
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bfe_dma_alloc(struct bfe_softc *sc)
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{
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struct bfe_dmamap_arg ctx;
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struct bfe_rx_data *rd;
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struct bfe_tx_data *td;
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int error, i;
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/*
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* parent tag. Apparently the chip cannot handle any DMA address
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* greater than 1GB.
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*/
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error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
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1, 0, /* alignment, boundary */
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BFE_DMA_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
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0, /* nsegments */
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BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->bfe_parent_tag);
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if (error != 0) {
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device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
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goto fail;
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}
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/* Create tag for Tx ring. */
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error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
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BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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BFE_TX_LIST_SIZE, /* maxsize */
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1, /* nsegments */
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BFE_TX_LIST_SIZE, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->bfe_tx_tag);
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if (error != 0) {
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device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
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goto fail;
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}
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/* Create tag for Rx ring. */
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error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
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BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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BFE_RX_LIST_SIZE, /* maxsize */
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1, /* nsegments */
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BFE_RX_LIST_SIZE, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->bfe_rx_tag);
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if (error != 0) {
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device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
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goto fail;
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}
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/* Create tag for Tx buffers. */
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error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
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1, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
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BFE_MAXTXSEGS, /* nsegments */
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MCLBYTES, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->bfe_txmbuf_tag);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot create Tx buffer DMA tag.\n");
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goto fail;
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}
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/* Create tag for Rx buffers. */
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error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
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1, 0, /* alignment, boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MCLBYTES, /* maxsize */
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1, /* nsegments */
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MCLBYTES, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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&sc->bfe_rxmbuf_tag);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot create Rx buffer DMA tag.\n");
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goto fail;
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}
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/* Allocate DMA'able memory and load DMA map. */
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error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
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BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot allocate DMA'able memory for Tx ring.\n");
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goto fail;
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}
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ctx.bfe_busaddr = 0;
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error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
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sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
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BUS_DMA_NOWAIT);
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if (error != 0 || ctx.bfe_busaddr == 0) {
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device_printf(sc->bfe_dev,
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"cannot load DMA'able memory for Tx ring.\n");
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goto fail;
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}
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sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
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error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
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BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot allocate DMA'able memory for Rx ring.\n");
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goto fail;
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}
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ctx.bfe_busaddr = 0;
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error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
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sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
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BUS_DMA_NOWAIT);
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if (error != 0 || ctx.bfe_busaddr == 0) {
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device_printf(sc->bfe_dev,
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"cannot load DMA'able memory for Rx ring.\n");
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goto fail;
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}
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sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
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|
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/* Create DMA maps for Tx buffers. */
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for (i = 0; i < BFE_TX_LIST_CNT; i++) {
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td = &sc->bfe_tx_ring[i];
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td->bfe_mbuf = NULL;
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td->bfe_map = NULL;
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error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot create DMA map for Tx.\n");
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goto fail;
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}
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}
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|
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/* Create spare DMA map for Rx buffers. */
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error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
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if (error != 0) {
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device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
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goto fail;
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}
|
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/* Create DMA maps for Rx buffers. */
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for (i = 0; i < BFE_RX_LIST_CNT; i++) {
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rd = &sc->bfe_rx_ring[i];
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rd->bfe_mbuf = NULL;
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rd->bfe_map = NULL;
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rd->bfe_ctrl = 0;
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error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
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if (error != 0) {
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device_printf(sc->bfe_dev,
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"cannot create DMA map for Rx.\n");
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goto fail;
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}
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}
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fail:
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return (error);
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}
|
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|
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static void
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bfe_dma_free(struct bfe_softc *sc)
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{
|
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struct bfe_tx_data *td;
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struct bfe_rx_data *rd;
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int i;
|
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/* Tx ring. */
|
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if (sc->bfe_tx_tag != NULL) {
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if (sc->bfe_tx_map != NULL)
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bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
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if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
|
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bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
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sc->bfe_tx_map);
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sc->bfe_tx_map = NULL;
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sc->bfe_tx_list = NULL;
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bus_dma_tag_destroy(sc->bfe_tx_tag);
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sc->bfe_tx_tag = NULL;
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}
|
|
|
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/* Rx ring. */
|
|
if (sc->bfe_rx_tag != NULL) {
|
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if (sc->bfe_rx_map != NULL)
|
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bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
|
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if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
|
|
bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
|
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sc->bfe_rx_map);
|
|
sc->bfe_rx_map = NULL;
|
|
sc->bfe_rx_list = NULL;
|
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bus_dma_tag_destroy(sc->bfe_rx_tag);
|
|
sc->bfe_rx_tag = NULL;
|
|
}
|
|
|
|
/* Tx buffers. */
|
|
if (sc->bfe_txmbuf_tag != NULL) {
|
|
for (i = 0; i < BFE_TX_LIST_CNT; i++) {
|
|
td = &sc->bfe_tx_ring[i];
|
|
if (td->bfe_map != NULL) {
|
|
bus_dmamap_destroy(sc->bfe_txmbuf_tag,
|
|
td->bfe_map);
|
|
td->bfe_map = NULL;
|
|
}
|
|
}
|
|
bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
|
|
sc->bfe_txmbuf_tag = NULL;
|
|
}
|
|
|
|
/* Rx buffers. */
|
|
if (sc->bfe_rxmbuf_tag != NULL) {
|
|
for (i = 0; i < BFE_RX_LIST_CNT; i++) {
|
|
rd = &sc->bfe_rx_ring[i];
|
|
if (rd->bfe_map != NULL) {
|
|
bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
|
|
rd->bfe_map);
|
|
rd->bfe_map = NULL;
|
|
}
|
|
}
|
|
if (sc->bfe_rx_sparemap != NULL) {
|
|
bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
|
|
sc->bfe_rx_sparemap);
|
|
sc->bfe_rx_sparemap = NULL;
|
|
}
|
|
bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
|
|
sc->bfe_rxmbuf_tag = NULL;
|
|
}
|
|
|
|
if (sc->bfe_parent_tag != NULL) {
|
|
bus_dma_tag_destroy(sc->bfe_parent_tag);
|
|
sc->bfe_parent_tag = NULL;
|
|
}
|
|
}
|
|
|
|
static int
|
|
bfe_attach(device_t dev)
|
|
{
|
|
struct ifnet *ifp = NULL;
|
|
struct bfe_softc *sc;
|
|
int error = 0, rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
|
MTX_DEF);
|
|
callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
|
|
|
|
sc->bfe_dev = dev;
|
|
|
|
/*
|
|
* Map control/status registers.
|
|
*/
|
|
pci_enable_busmaster(dev);
|
|
|
|
rid = PCIR_BAR(0);
|
|
sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->bfe_res == NULL) {
|
|
device_printf(dev, "couldn't map memory\n");
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/* Allocate interrupt */
|
|
rid = 0;
|
|
|
|
sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
if (sc->bfe_irq == NULL) {
|
|
device_printf(dev, "couldn't map interrupt\n");
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
if (bfe_dma_alloc(sc) != 0) {
|
|
device_printf(dev, "failed to allocate DMA resources\n");
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/* Set up ifnet structure */
|
|
ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
|
|
if (ifp == NULL) {
|
|
device_printf(dev, "failed to if_alloc()\n");
|
|
error = ENOSPC;
|
|
goto fail;
|
|
}
|
|
ifp->if_softc = sc;
|
|
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
ifp->if_ioctl = bfe_ioctl;
|
|
ifp->if_start = bfe_start;
|
|
ifp->if_init = bfe_init;
|
|
ifp->if_mtu = ETHERMTU;
|
|
IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
|
|
ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
|
|
IFQ_SET_READY(&ifp->if_snd);
|
|
|
|
bfe_get_config(sc);
|
|
|
|
/* Reset the chip and turn on the PHY */
|
|
BFE_LOCK(sc);
|
|
bfe_chip_reset(sc);
|
|
BFE_UNLOCK(sc);
|
|
|
|
if (mii_phy_probe(dev, &sc->bfe_miibus,
|
|
bfe_ifmedia_upd, bfe_ifmedia_sts)) {
|
|
device_printf(dev, "MII without any PHY!\n");
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
ether_ifattach(ifp, sc->bfe_enaddr);
|
|
|
|
/*
|
|
* Tell the upper layer(s) we support long frames.
|
|
*/
|
|
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
|
|
ifp->if_capabilities |= IFCAP_VLAN_MTU;
|
|
ifp->if_capenable |= IFCAP_VLAN_MTU;
|
|
|
|
/*
|
|
* Hook interrupt last to avoid having to lock softc
|
|
*/
|
|
error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
|
|
NULL, bfe_intr, sc, &sc->bfe_intrhand);
|
|
|
|
if (error) {
|
|
device_printf(dev, "couldn't set up irq\n");
|
|
goto fail;
|
|
}
|
|
fail:
|
|
if (error != 0)
|
|
bfe_detach(dev);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
bfe_detach(device_t dev)
|
|
{
|
|
struct bfe_softc *sc;
|
|
struct ifnet *ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
ifp = sc->bfe_ifp;
|
|
|
|
if (device_is_attached(dev)) {
|
|
BFE_LOCK(sc);
|
|
sc->bfe_flags |= BFE_FLAG_DETACH;
|
|
bfe_stop(sc);
|
|
BFE_UNLOCK(sc);
|
|
callout_drain(&sc->bfe_stat_co);
|
|
if (ifp != NULL)
|
|
ether_ifdetach(ifp);
|
|
}
|
|
|
|
BFE_LOCK(sc);
|
|
bfe_chip_reset(sc);
|
|
BFE_UNLOCK(sc);
|
|
|
|
bus_generic_detach(dev);
|
|
if (sc->bfe_miibus != NULL)
|
|
device_delete_child(dev, sc->bfe_miibus);
|
|
|
|
bfe_release_resources(sc);
|
|
bfe_dma_free(sc);
|
|
mtx_destroy(&sc->bfe_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Stop all chip I/O so that the kernel's probe routines don't
|
|
* get confused by errant DMAs when rebooting.
|
|
*/
|
|
static int
|
|
bfe_shutdown(device_t dev)
|
|
{
|
|
struct bfe_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
BFE_LOCK(sc);
|
|
bfe_stop(sc);
|
|
|
|
BFE_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bfe_suspend(device_t dev)
|
|
{
|
|
struct bfe_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
BFE_LOCK(sc);
|
|
bfe_stop(sc);
|
|
BFE_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bfe_resume(device_t dev)
|
|
{
|
|
struct bfe_softc *sc;
|
|
struct ifnet *ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
ifp = sc->bfe_ifp;
|
|
BFE_LOCK(sc);
|
|
bfe_chip_reset(sc);
|
|
if (ifp->if_flags & IFF_UP) {
|
|
bfe_init_locked(sc);
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
|
|
!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
|
bfe_start_locked(ifp);
|
|
}
|
|
BFE_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bfe_miibus_readreg(device_t dev, int phy, int reg)
|
|
{
|
|
struct bfe_softc *sc;
|
|
u_int32_t ret;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (phy != sc->bfe_phyaddr)
|
|
return (0);
|
|
bfe_readphy(sc, reg, &ret);
|
|
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
|
|
{
|
|
struct bfe_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (phy != sc->bfe_phyaddr)
|
|
return (0);
|
|
bfe_writephy(sc, reg, val);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bfe_miibus_statchg(device_t dev)
|
|
{
|
|
struct bfe_softc *sc;
|
|
struct mii_data *mii;
|
|
u_int32_t val, flow;
|
|
|
|
sc = device_get_softc(dev);
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
|
|
sc->bfe_flags &= ~BFE_FLAG_LINK;
|
|
if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
|
|
(IFM_ACTIVE | IFM_AVALID)) {
|
|
switch (IFM_SUBTYPE(mii->mii_media_active)) {
|
|
case IFM_10_T:
|
|
case IFM_100_TX:
|
|
sc->bfe_flags |= BFE_FLAG_LINK;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* XXX Should stop Rx/Tx engine prior to touching MAC. */
|
|
val = CSR_READ_4(sc, BFE_TX_CTRL);
|
|
val &= ~BFE_TX_DUPLEX;
|
|
if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
|
|
val |= BFE_TX_DUPLEX;
|
|
flow = 0;
|
|
#ifdef notyet
|
|
flow = CSR_READ_4(sc, BFE_RXCONF);
|
|
flow &= ~BFE_RXCONF_FLOW;
|
|
if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
|
|
IFM_ETH_RXPAUSE) != 0)
|
|
flow |= BFE_RXCONF_FLOW;
|
|
CSR_WRITE_4(sc, BFE_RXCONF, flow);
|
|
/*
|
|
* It seems that the hardware has Tx pause issues
|
|
* so enable only Rx pause.
|
|
*/
|
|
flow = CSR_READ_4(sc, BFE_MAC_FLOW);
|
|
flow &= ~BFE_FLOW_PAUSE_ENAB;
|
|
CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
|
|
#endif
|
|
}
|
|
CSR_WRITE_4(sc, BFE_TX_CTRL, val);
|
|
}
|
|
|
|
static void
|
|
bfe_tx_ring_free(struct bfe_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
for(i = 0; i < BFE_TX_LIST_CNT; i++) {
|
|
if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
|
|
bus_dmamap_sync(sc->bfe_txmbuf_tag,
|
|
sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->bfe_txmbuf_tag,
|
|
sc->bfe_tx_ring[i].bfe_map);
|
|
m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
|
|
sc->bfe_tx_ring[i].bfe_mbuf = NULL;
|
|
}
|
|
}
|
|
bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
|
|
bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
}
|
|
|
|
static void
|
|
bfe_rx_ring_free(struct bfe_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < BFE_RX_LIST_CNT; i++) {
|
|
if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
|
|
bus_dmamap_sync(sc->bfe_rxmbuf_tag,
|
|
sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
|
|
bus_dmamap_unload(sc->bfe_rxmbuf_tag,
|
|
sc->bfe_rx_ring[i].bfe_map);
|
|
m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
|
|
sc->bfe_rx_ring[i].bfe_mbuf = NULL;
|
|
}
|
|
}
|
|
bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
|
|
bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
}
|
|
|
|
static int
|
|
bfe_list_rx_init(struct bfe_softc *sc)
|
|
{
|
|
struct bfe_rx_data *rd;
|
|
int i;
|
|
|
|
sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
|
|
bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
|
|
for (i = 0; i < BFE_RX_LIST_CNT; i++) {
|
|
rd = &sc->bfe_rx_ring[i];
|
|
rd->bfe_mbuf = NULL;
|
|
rd->bfe_ctrl = 0;
|
|
if (bfe_list_newbuf(sc, i) != 0)
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bfe_list_tx_init(struct bfe_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
|
|
bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
|
|
for (i = 0; i < BFE_TX_LIST_CNT; i++)
|
|
sc->bfe_tx_ring[i].bfe_mbuf = NULL;
|
|
|
|
bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
}
|
|
|
|
static void
|
|
bfe_discard_buf(struct bfe_softc *sc, int c)
|
|
{
|
|
struct bfe_rx_data *r;
|
|
struct bfe_desc *d;
|
|
|
|
r = &sc->bfe_rx_ring[c];
|
|
d = &sc->bfe_rx_list[c];
|
|
d->bfe_ctrl = htole32(r->bfe_ctrl);
|
|
}
|
|
|
|
static int
|
|
bfe_list_newbuf(struct bfe_softc *sc, int c)
|
|
{
|
|
struct bfe_rxheader *rx_header;
|
|
struct bfe_desc *d;
|
|
struct bfe_rx_data *r;
|
|
struct mbuf *m;
|
|
bus_dma_segment_t segs[1];
|
|
bus_dmamap_t map;
|
|
u_int32_t ctrl;
|
|
int nsegs;
|
|
|
|
m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
|
|
m->m_len = m->m_pkthdr.len = MCLBYTES;
|
|
|
|
if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
|
|
m, segs, &nsegs, 0) != 0) {
|
|
m_freem(m);
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
|
|
r = &sc->bfe_rx_ring[c];
|
|
if (r->bfe_mbuf != NULL) {
|
|
bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
|
|
}
|
|
map = r->bfe_map;
|
|
r->bfe_map = sc->bfe_rx_sparemap;
|
|
sc->bfe_rx_sparemap = map;
|
|
r->bfe_mbuf = m;
|
|
|
|
rx_header = mtod(m, struct bfe_rxheader *);
|
|
rx_header->len = 0;
|
|
rx_header->flags = 0;
|
|
bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
|
|
|
|
ctrl = segs[0].ds_len & BFE_DESC_LEN;
|
|
KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
|
|
__func__, ctrl));
|
|
if (c == BFE_RX_LIST_CNT - 1)
|
|
ctrl |= BFE_DESC_EOT;
|
|
r->bfe_ctrl = ctrl;
|
|
|
|
d = &sc->bfe_rx_list[c];
|
|
d->bfe_ctrl = htole32(ctrl);
|
|
/* The chip needs all addresses to be added to BFE_PCI_DMA. */
|
|
d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bfe_get_config(struct bfe_softc *sc)
|
|
{
|
|
u_int8_t eeprom[128];
|
|
|
|
bfe_read_eeprom(sc, eeprom);
|
|
|
|
sc->bfe_enaddr[0] = eeprom[79];
|
|
sc->bfe_enaddr[1] = eeprom[78];
|
|
sc->bfe_enaddr[2] = eeprom[81];
|
|
sc->bfe_enaddr[3] = eeprom[80];
|
|
sc->bfe_enaddr[4] = eeprom[83];
|
|
sc->bfe_enaddr[5] = eeprom[82];
|
|
|
|
sc->bfe_phyaddr = eeprom[90] & 0x1f;
|
|
sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
|
|
|
|
sc->bfe_core_unit = 0;
|
|
sc->bfe_dma_offset = BFE_PCI_DMA;
|
|
}
|
|
|
|
static void
|
|
bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
|
|
{
|
|
u_int32_t bar_orig, pci_rev, val;
|
|
|
|
bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
|
|
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
|
|
pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
|
|
|
|
val = CSR_READ_4(sc, BFE_SBINTVEC);
|
|
val |= cores;
|
|
CSR_WRITE_4(sc, BFE_SBINTVEC, val);
|
|
|
|
val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
|
|
val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
|
|
CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
|
|
|
|
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
|
|
}
|
|
|
|
static void
|
|
bfe_clear_stats(struct bfe_softc *sc)
|
|
{
|
|
u_long reg;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
|
|
for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
|
|
CSR_READ_4(sc, reg);
|
|
for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
|
|
CSR_READ_4(sc, reg);
|
|
}
|
|
|
|
static int
|
|
bfe_resetphy(struct bfe_softc *sc)
|
|
{
|
|
u_int32_t val;
|
|
|
|
bfe_writephy(sc, 0, BMCR_RESET);
|
|
DELAY(100);
|
|
bfe_readphy(sc, 0, &val);
|
|
if (val & BMCR_RESET) {
|
|
device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
|
|
return (ENXIO);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bfe_chip_halt(struct bfe_softc *sc)
|
|
{
|
|
BFE_LOCK_ASSERT(sc);
|
|
/* disable interrupts - not that it actually does..*/
|
|
CSR_WRITE_4(sc, BFE_IMASK, 0);
|
|
CSR_READ_4(sc, BFE_IMASK);
|
|
|
|
CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
|
|
bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
|
|
|
|
CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
|
|
CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
|
|
DELAY(10);
|
|
}
|
|
|
|
static void
|
|
bfe_chip_reset(struct bfe_softc *sc)
|
|
{
|
|
u_int32_t val;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
/* Set the interrupt vector for the enet core */
|
|
bfe_pci_setup(sc, BFE_INTVEC_ENET0);
|
|
|
|
/* is core up? */
|
|
val = CSR_READ_4(sc, BFE_SBTMSLOW) &
|
|
(BFE_RESET | BFE_REJECT | BFE_CLOCK);
|
|
if (val == BFE_CLOCK) {
|
|
/* It is, so shut it down */
|
|
CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
|
|
CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
|
|
bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
|
|
CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
|
|
if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
|
|
bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
|
|
100, 0);
|
|
CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
|
|
}
|
|
|
|
bfe_core_reset(sc);
|
|
bfe_clear_stats(sc);
|
|
|
|
/*
|
|
* We want the phy registers to be accessible even when
|
|
* the driver is "downed" so initialize MDC preamble, frequency,
|
|
* and whether internal or external phy here.
|
|
*/
|
|
|
|
/* 4402 has 62.5Mhz SB clock and internal phy */
|
|
CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
|
|
|
|
/* Internal or external PHY? */
|
|
val = CSR_READ_4(sc, BFE_DEVCTRL);
|
|
if (!(val & BFE_IPP))
|
|
CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
|
|
else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
|
|
BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
|
|
DELAY(100);
|
|
}
|
|
|
|
/* Enable CRC32 generation and set proper LED modes */
|
|
BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
|
|
|
|
/* Reset or clear powerdown control bit */
|
|
BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
|
|
|
|
CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
|
|
BFE_LAZY_FC_MASK));
|
|
|
|
/*
|
|
* We don't want lazy interrupts, so just send them at
|
|
* the end of a frame, please
|
|
*/
|
|
BFE_OR(sc, BFE_RCV_LAZY, 0);
|
|
|
|
/* Set max lengths, accounting for VLAN tags */
|
|
CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
|
|
CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
|
|
|
|
/* Set watermark XXX - magic */
|
|
CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
|
|
|
|
/*
|
|
* Initialise DMA channels
|
|
* - not forgetting dma addresses need to be added to BFE_PCI_DMA
|
|
*/
|
|
CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
|
|
CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
|
|
|
|
CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
|
|
BFE_RX_CTRL_ENABLE);
|
|
CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
|
|
|
|
bfe_resetphy(sc);
|
|
bfe_setupphy(sc);
|
|
}
|
|
|
|
static void
|
|
bfe_core_disable(struct bfe_softc *sc)
|
|
{
|
|
if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
|
|
return;
|
|
|
|
/*
|
|
* Set reject, wait for it set, then wait for the core to stop
|
|
* being busy, then set reset and reject and enable the clocks.
|
|
*/
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
|
|
bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
|
|
bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
|
|
BFE_RESET));
|
|
CSR_READ_4(sc, BFE_SBTMSLOW);
|
|
DELAY(10);
|
|
/* Leave reset and reject set */
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
|
|
DELAY(10);
|
|
}
|
|
|
|
static void
|
|
bfe_core_reset(struct bfe_softc *sc)
|
|
{
|
|
u_int32_t val;
|
|
|
|
/* Disable the core */
|
|
bfe_core_disable(sc);
|
|
|
|
/* and bring it back up */
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
|
|
CSR_READ_4(sc, BFE_SBTMSLOW);
|
|
DELAY(10);
|
|
|
|
/* Chip bug, clear SERR, IB and TO if they are set. */
|
|
if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
|
|
CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
|
|
val = CSR_READ_4(sc, BFE_SBIMSTATE);
|
|
if (val & (BFE_IBE | BFE_TO))
|
|
CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
|
|
|
|
/* Clear reset and allow it to move through the core */
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
|
|
CSR_READ_4(sc, BFE_SBTMSLOW);
|
|
DELAY(10);
|
|
|
|
/* Leave the clock set */
|
|
CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
|
|
CSR_READ_4(sc, BFE_SBTMSLOW);
|
|
DELAY(10);
|
|
}
|
|
|
|
static void
|
|
bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
|
|
{
|
|
u_int32_t val;
|
|
|
|
val = ((u_int32_t) data[2]) << 24;
|
|
val |= ((u_int32_t) data[3]) << 16;
|
|
val |= ((u_int32_t) data[4]) << 8;
|
|
val |= ((u_int32_t) data[5]);
|
|
CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
|
|
val = (BFE_CAM_HI_VALID |
|
|
(((u_int32_t) data[0]) << 8) |
|
|
(((u_int32_t) data[1])));
|
|
CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
|
|
CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
|
|
((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
|
|
bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
|
|
}
|
|
|
|
static void
|
|
bfe_set_rx_mode(struct bfe_softc *sc)
|
|
{
|
|
struct ifnet *ifp = sc->bfe_ifp;
|
|
struct ifmultiaddr *ifma;
|
|
u_int32_t val;
|
|
int i = 0;
|
|
|
|
val = CSR_READ_4(sc, BFE_RXCONF);
|
|
|
|
if (ifp->if_flags & IFF_PROMISC)
|
|
val |= BFE_RXCONF_PROMISC;
|
|
else
|
|
val &= ~BFE_RXCONF_PROMISC;
|
|
|
|
if (ifp->if_flags & IFF_BROADCAST)
|
|
val &= ~BFE_RXCONF_DBCAST;
|
|
else
|
|
val |= BFE_RXCONF_DBCAST;
|
|
|
|
|
|
CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
|
|
bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
|
|
|
|
if (ifp->if_flags & IFF_ALLMULTI)
|
|
val |= BFE_RXCONF_ALLMULTI;
|
|
else {
|
|
val &= ~BFE_RXCONF_ALLMULTI;
|
|
IF_ADDR_LOCK(ifp);
|
|
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
|
if (ifma->ifma_addr->sa_family != AF_LINK)
|
|
continue;
|
|
bfe_cam_write(sc,
|
|
LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
|
|
}
|
|
IF_ADDR_UNLOCK(ifp);
|
|
}
|
|
|
|
CSR_WRITE_4(sc, BFE_RXCONF, val);
|
|
BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
|
|
}
|
|
|
|
static void
|
|
bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
struct bfe_dmamap_arg *ctx;
|
|
|
|
if (error != 0)
|
|
return;
|
|
|
|
KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
|
|
|
|
ctx = (struct bfe_dmamap_arg *)arg;
|
|
ctx->bfe_busaddr = segs[0].ds_addr;
|
|
}
|
|
|
|
static void
|
|
bfe_release_resources(struct bfe_softc *sc)
|
|
{
|
|
|
|
if (sc->bfe_intrhand != NULL)
|
|
bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
|
|
|
|
if (sc->bfe_irq != NULL)
|
|
bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
|
|
|
|
if (sc->bfe_res != NULL)
|
|
bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
|
|
sc->bfe_res);
|
|
|
|
if (sc->bfe_ifp != NULL)
|
|
if_free(sc->bfe_ifp);
|
|
}
|
|
|
|
static void
|
|
bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
|
|
{
|
|
long i;
|
|
u_int16_t *ptr = (u_int16_t *)data;
|
|
|
|
for(i = 0; i < 128; i += 2)
|
|
ptr[i/2] = CSR_READ_4(sc, 4096 + i);
|
|
}
|
|
|
|
static int
|
|
bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
|
|
u_long timeout, const int clear)
|
|
{
|
|
u_long i;
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
u_int32_t val = CSR_READ_4(sc, reg);
|
|
|
|
if (clear && !(val & bit))
|
|
break;
|
|
if (!clear && (val & bit))
|
|
break;
|
|
DELAY(10);
|
|
}
|
|
if (i == timeout) {
|
|
device_printf(sc->bfe_dev,
|
|
"BUG! Timeout waiting for bit %08x of register "
|
|
"%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
|
|
return (-1);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
|
|
{
|
|
int err;
|
|
|
|
/* Clear MII ISR */
|
|
CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
|
|
CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
|
|
(BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
|
|
(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
|
|
(reg << BFE_MDIO_RA_SHIFT) |
|
|
(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
|
|
err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
|
|
*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
|
|
|
|
return (err);
|
|
}
|
|
|
|
static int
|
|
bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
|
|
{
|
|
int status;
|
|
|
|
CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
|
|
CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
|
|
(BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
|
|
(sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
|
|
(reg << BFE_MDIO_RA_SHIFT) |
|
|
(BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
|
|
(val & BFE_MDIO_DATA_DATA)));
|
|
status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
|
|
|
|
return (status);
|
|
}
|
|
|
|
/*
|
|
* XXX - I think this is handled by the PHY driver, but it can't hurt to do it
|
|
* twice
|
|
*/
|
|
static int
|
|
bfe_setupphy(struct bfe_softc *sc)
|
|
{
|
|
u_int32_t val;
|
|
|
|
/* Enable activity LED */
|
|
bfe_readphy(sc, 26, &val);
|
|
bfe_writephy(sc, 26, val & 0x7fff);
|
|
bfe_readphy(sc, 26, &val);
|
|
|
|
/* Enable traffic meter LED mode */
|
|
bfe_readphy(sc, 27, &val);
|
|
bfe_writephy(sc, 27, val | (1 << 6));
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bfe_stats_update(struct bfe_softc *sc)
|
|
{
|
|
u_long reg;
|
|
u_int32_t *val;
|
|
|
|
val = &sc->bfe_hwstats.tx_good_octets;
|
|
for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) {
|
|
*val++ += CSR_READ_4(sc, reg);
|
|
}
|
|
val = &sc->bfe_hwstats.rx_good_octets;
|
|
for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) {
|
|
*val++ += CSR_READ_4(sc, reg);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bfe_txeof(struct bfe_softc *sc)
|
|
{
|
|
struct bfe_tx_data *r;
|
|
struct ifnet *ifp;
|
|
int i, chipidx;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
ifp = sc->bfe_ifp;
|
|
|
|
chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
|
|
chipidx /= sizeof(struct bfe_desc);
|
|
|
|
i = sc->bfe_tx_cons;
|
|
if (i == chipidx)
|
|
return;
|
|
bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
|
|
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
|
/* Go through the mbufs and free those that have been transmitted */
|
|
for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
|
|
r = &sc->bfe_tx_ring[i];
|
|
sc->bfe_tx_cnt--;
|
|
if (r->bfe_mbuf == NULL)
|
|
continue;
|
|
bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
|
|
BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
|
|
|
|
ifp->if_opackets++;
|
|
m_freem(r->bfe_mbuf);
|
|
r->bfe_mbuf = NULL;
|
|
}
|
|
|
|
if (i != sc->bfe_tx_cons) {
|
|
/* we freed up some mbufs */
|
|
sc->bfe_tx_cons = i;
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
|
}
|
|
|
|
if (sc->bfe_tx_cnt == 0)
|
|
sc->bfe_watchdog_timer = 0;
|
|
}
|
|
|
|
/* Pass a received packet up the stack */
|
|
static void
|
|
bfe_rxeof(struct bfe_softc *sc)
|
|
{
|
|
struct mbuf *m;
|
|
struct ifnet *ifp;
|
|
struct bfe_rxheader *rxheader;
|
|
struct bfe_rx_data *r;
|
|
int cons, prog;
|
|
u_int32_t status, current, len, flags;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
cons = sc->bfe_rx_cons;
|
|
status = CSR_READ_4(sc, BFE_DMARX_STAT);
|
|
current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
|
|
|
|
ifp = sc->bfe_ifp;
|
|
|
|
bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
|
|
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
|
|
|
for (prog = 0; current != cons; prog++,
|
|
BFE_INC(cons, BFE_RX_LIST_CNT)) {
|
|
r = &sc->bfe_rx_ring[cons];
|
|
m = r->bfe_mbuf;
|
|
/*
|
|
* Rx status should be read from mbuf such that we can't
|
|
* delay bus_dmamap_sync(9). This hardware limiation
|
|
* results in inefficent mbuf usage as bfe(4) couldn't
|
|
* reuse mapped buffer from errored frame.
|
|
*/
|
|
if (bfe_list_newbuf(sc, cons) != 0) {
|
|
ifp->if_iqdrops++;
|
|
bfe_discard_buf(sc, cons);
|
|
continue;
|
|
}
|
|
rxheader = mtod(m, struct bfe_rxheader*);
|
|
len = le16toh(rxheader->len);
|
|
flags = le16toh(rxheader->flags);
|
|
|
|
/* Remove CRC bytes. */
|
|
len -= ETHER_CRC_LEN;
|
|
|
|
/* flag an error and try again */
|
|
if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
|
|
ifp->if_ierrors++;
|
|
if (flags & BFE_RX_FLAG_SERR)
|
|
ifp->if_collisions++;
|
|
m_freem(m);
|
|
continue;
|
|
}
|
|
|
|
/* Make sure to skip header bytes written by hardware. */
|
|
m_adj(m, BFE_RX_OFFSET);
|
|
m->m_len = m->m_pkthdr.len = len;
|
|
|
|
ifp->if_ipackets++;
|
|
m->m_pkthdr.rcvif = ifp;
|
|
BFE_UNLOCK(sc);
|
|
(*ifp->if_input)(ifp, m);
|
|
BFE_LOCK(sc);
|
|
}
|
|
|
|
if (prog > 0) {
|
|
sc->bfe_rx_cons = cons;
|
|
bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bfe_intr(void *xsc)
|
|
{
|
|
struct bfe_softc *sc = xsc;
|
|
struct ifnet *ifp;
|
|
u_int32_t istat, imask, flag;
|
|
|
|
ifp = sc->bfe_ifp;
|
|
|
|
BFE_LOCK(sc);
|
|
|
|
istat = CSR_READ_4(sc, BFE_ISTAT);
|
|
imask = CSR_READ_4(sc, BFE_IMASK);
|
|
|
|
/*
|
|
* Defer unsolicited interrupts - This is necessary because setting the
|
|
* chips interrupt mask register to 0 doesn't actually stop the
|
|
* interrupts
|
|
*/
|
|
istat &= imask;
|
|
CSR_WRITE_4(sc, BFE_ISTAT, istat);
|
|
CSR_READ_4(sc, BFE_ISTAT);
|
|
|
|
/* not expecting this interrupt, disregard it */
|
|
if (istat == 0) {
|
|
BFE_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
if (istat & BFE_ISTAT_ERRORS) {
|
|
|
|
if (istat & BFE_ISTAT_DSCE) {
|
|
device_printf(sc->bfe_dev, "Descriptor Error\n");
|
|
bfe_stop(sc);
|
|
BFE_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
if (istat & BFE_ISTAT_DPE) {
|
|
device_printf(sc->bfe_dev,
|
|
"Descriptor Protocol Error\n");
|
|
bfe_stop(sc);
|
|
BFE_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
flag = CSR_READ_4(sc, BFE_DMATX_STAT);
|
|
if (flag & BFE_STAT_EMASK)
|
|
ifp->if_oerrors++;
|
|
|
|
flag = CSR_READ_4(sc, BFE_DMARX_STAT);
|
|
if (flag & BFE_RX_FLAG_ERRORS)
|
|
ifp->if_ierrors++;
|
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
|
|
bfe_init_locked(sc);
|
|
}
|
|
|
|
/* A packet was received */
|
|
if (istat & BFE_ISTAT_RX)
|
|
bfe_rxeof(sc);
|
|
|
|
/* A packet was sent */
|
|
if (istat & BFE_ISTAT_TX)
|
|
bfe_txeof(sc);
|
|
|
|
/* We have packets pending, fire them out */
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
|
|
!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
|
bfe_start_locked(ifp);
|
|
|
|
BFE_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
|
|
{
|
|
struct bfe_desc *d;
|
|
struct bfe_tx_data *r, *r1;
|
|
struct mbuf *m;
|
|
bus_dmamap_t map;
|
|
bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
|
|
uint32_t cur, si;
|
|
int error, i, nsegs;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
M_ASSERTPKTHDR((*m_head));
|
|
|
|
si = cur = sc->bfe_tx_prod;
|
|
r = &sc->bfe_tx_ring[cur];
|
|
error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
|
|
txsegs, &nsegs, 0);
|
|
if (error == EFBIG) {
|
|
m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS);
|
|
if (m == NULL) {
|
|
m_freem(*m_head);
|
|
*m_head = NULL;
|
|
return (ENOMEM);
|
|
}
|
|
*m_head = m;
|
|
error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
|
|
*m_head, txsegs, &nsegs, 0);
|
|
if (error != 0) {
|
|
m_freem(*m_head);
|
|
*m_head = NULL;
|
|
return (error);
|
|
}
|
|
} else if (error != 0)
|
|
return (error);
|
|
if (nsegs == 0) {
|
|
m_freem(*m_head);
|
|
*m_head = NULL;
|
|
return (EIO);
|
|
}
|
|
|
|
if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
|
|
bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
for (i = 0; i < nsegs; i++) {
|
|
d = &sc->bfe_tx_list[cur];
|
|
d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
|
|
d->bfe_ctrl |= htole32(BFE_DESC_IOC);
|
|
if (cur == BFE_TX_LIST_CNT - 1)
|
|
/*
|
|
* Tell the chip to wrap to the start of
|
|
* the descriptor list.
|
|
*/
|
|
d->bfe_ctrl |= htole32(BFE_DESC_EOT);
|
|
/* The chip needs all addresses to be added to BFE_PCI_DMA. */
|
|
d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
|
|
BFE_PCI_DMA);
|
|
BFE_INC(cur, BFE_TX_LIST_CNT);
|
|
}
|
|
|
|
/* Update producer index. */
|
|
sc->bfe_tx_prod = cur;
|
|
|
|
/* Set EOF on the last descriptor. */
|
|
cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
|
|
d = &sc->bfe_tx_list[cur];
|
|
d->bfe_ctrl |= htole32(BFE_DESC_EOF);
|
|
|
|
/* Lastly set SOF on the first descriptor to avoid races. */
|
|
d = &sc->bfe_tx_list[si];
|
|
d->bfe_ctrl |= htole32(BFE_DESC_SOF);
|
|
|
|
r1 = &sc->bfe_tx_ring[cur];
|
|
map = r->bfe_map;
|
|
r->bfe_map = r1->bfe_map;
|
|
r1->bfe_map = map;
|
|
r1->bfe_mbuf = *m_head;
|
|
sc->bfe_tx_cnt += nsegs;
|
|
|
|
bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Set up to transmit a packet.
|
|
*/
|
|
static void
|
|
bfe_start(struct ifnet *ifp)
|
|
{
|
|
BFE_LOCK((struct bfe_softc *)ifp->if_softc);
|
|
bfe_start_locked(ifp);
|
|
BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
|
|
}
|
|
|
|
/*
|
|
* Set up to transmit a packet. The softc is already locked.
|
|
*/
|
|
static void
|
|
bfe_start_locked(struct ifnet *ifp)
|
|
{
|
|
struct bfe_softc *sc;
|
|
struct mbuf *m_head;
|
|
int queued;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
/*
|
|
* Not much point trying to send if the link is down
|
|
* or we have nothing to send.
|
|
*/
|
|
if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
|
|
IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
|
|
return;
|
|
|
|
for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
|
|
sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
|
|
IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
|
|
if (m_head == NULL)
|
|
break;
|
|
|
|
/*
|
|
* Pack the data into the tx ring. If we dont have
|
|
* enough room, let the chip drain the ring.
|
|
*/
|
|
if (bfe_encap(sc, &m_head)) {
|
|
if (m_head == NULL)
|
|
break;
|
|
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
|
|
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
|
break;
|
|
}
|
|
|
|
queued++;
|
|
|
|
/*
|
|
* If there's a BPF listener, bounce a copy of this frame
|
|
* to him.
|
|
*/
|
|
BPF_MTAP(ifp, m_head);
|
|
}
|
|
|
|
if (queued) {
|
|
bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
|
|
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
|
/* Transmit - twice due to apparent hardware bug */
|
|
CSR_WRITE_4(sc, BFE_DMATX_PTR,
|
|
sc->bfe_tx_prod * sizeof(struct bfe_desc));
|
|
/*
|
|
* XXX It seems the following write is not necessary
|
|
* to kick Tx command. What might be required would be
|
|
* a way flushing PCI posted write. Reading the register
|
|
* back ensures the flush operation. In addition,
|
|
* hardware will execute PCI posted write in the long
|
|
* run and watchdog timer for the kick command was set
|
|
* to 5 seconds. Therefore I think the second write
|
|
* access is not necessary or could be replaced with
|
|
* read operation.
|
|
*/
|
|
CSR_WRITE_4(sc, BFE_DMATX_PTR,
|
|
sc->bfe_tx_prod * sizeof(struct bfe_desc));
|
|
|
|
/*
|
|
* Set a timeout in case the chip goes out to lunch.
|
|
*/
|
|
sc->bfe_watchdog_timer = 5;
|
|
}
|
|
}
|
|
|
|
static void
|
|
bfe_init(void *xsc)
|
|
{
|
|
BFE_LOCK((struct bfe_softc *)xsc);
|
|
bfe_init_locked(xsc);
|
|
BFE_UNLOCK((struct bfe_softc *)xsc);
|
|
}
|
|
|
|
static void
|
|
bfe_init_locked(void *xsc)
|
|
{
|
|
struct bfe_softc *sc = (struct bfe_softc*)xsc;
|
|
struct ifnet *ifp = sc->bfe_ifp;
|
|
struct mii_data *mii;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
|
return;
|
|
|
|
bfe_stop(sc);
|
|
bfe_chip_reset(sc);
|
|
|
|
if (bfe_list_rx_init(sc) == ENOBUFS) {
|
|
device_printf(sc->bfe_dev,
|
|
"%s: Not enough memory for list buffers\n", __func__);
|
|
bfe_stop(sc);
|
|
return;
|
|
}
|
|
bfe_list_tx_init(sc);
|
|
|
|
bfe_set_rx_mode(sc);
|
|
|
|
/* Enable the chip and core */
|
|
BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
|
|
/* Enable interrupts */
|
|
CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
|
|
|
|
/* Clear link state and change media. */
|
|
sc->bfe_flags &= ~BFE_FLAG_LINK;
|
|
mii_mediachg(mii);
|
|
|
|
ifp->if_drv_flags |= IFF_DRV_RUNNING;
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
|
|
|
callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
|
|
}
|
|
|
|
/*
|
|
* Set media options.
|
|
*/
|
|
static int
|
|
bfe_ifmedia_upd(struct ifnet *ifp)
|
|
{
|
|
struct bfe_softc *sc;
|
|
struct mii_data *mii;
|
|
int error;
|
|
|
|
sc = ifp->if_softc;
|
|
BFE_LOCK(sc);
|
|
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
if (mii->mii_instance) {
|
|
struct mii_softc *miisc;
|
|
for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
|
|
miisc = LIST_NEXT(miisc, mii_list))
|
|
mii_phy_reset(miisc);
|
|
}
|
|
error = mii_mediachg(mii);
|
|
BFE_UNLOCK(sc);
|
|
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Report current media status.
|
|
*/
|
|
static void
|
|
bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
|
|
{
|
|
struct bfe_softc *sc = ifp->if_softc;
|
|
struct mii_data *mii;
|
|
|
|
BFE_LOCK(sc);
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
mii_pollstat(mii);
|
|
ifmr->ifm_active = mii->mii_media_active;
|
|
ifmr->ifm_status = mii->mii_media_status;
|
|
BFE_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
|
|
{
|
|
struct bfe_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *) data;
|
|
struct mii_data *mii;
|
|
int error = 0;
|
|
|
|
switch (command) {
|
|
case SIOCSIFFLAGS:
|
|
BFE_LOCK(sc);
|
|
if (ifp->if_flags & IFF_UP) {
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
|
bfe_set_rx_mode(sc);
|
|
else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
|
|
bfe_init_locked(sc);
|
|
} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
|
bfe_stop(sc);
|
|
BFE_UNLOCK(sc);
|
|
break;
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
BFE_LOCK(sc);
|
|
if (ifp->if_drv_flags & IFF_DRV_RUNNING)
|
|
bfe_set_rx_mode(sc);
|
|
BFE_UNLOCK(sc);
|
|
break;
|
|
case SIOCGIFMEDIA:
|
|
case SIOCSIFMEDIA:
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
|
|
break;
|
|
default:
|
|
error = ether_ioctl(ifp, command, data);
|
|
break;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
bfe_watchdog(struct bfe_softc *sc)
|
|
{
|
|
struct ifnet *ifp;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
|
|
return;
|
|
|
|
ifp = sc->bfe_ifp;
|
|
|
|
device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
|
|
|
|
ifp->if_oerrors++;
|
|
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
|
|
bfe_init_locked(sc);
|
|
|
|
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
|
bfe_start_locked(ifp);
|
|
}
|
|
|
|
static void
|
|
bfe_tick(void *xsc)
|
|
{
|
|
struct bfe_softc *sc = xsc;
|
|
struct mii_data *mii;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
mii = device_get_softc(sc->bfe_miibus);
|
|
mii_tick(mii);
|
|
bfe_stats_update(sc);
|
|
bfe_watchdog(sc);
|
|
callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
|
|
}
|
|
|
|
/*
|
|
* Stop the adapter and free any mbufs allocated to the
|
|
* RX and TX lists.
|
|
*/
|
|
static void
|
|
bfe_stop(struct bfe_softc *sc)
|
|
{
|
|
struct ifnet *ifp;
|
|
|
|
BFE_LOCK_ASSERT(sc);
|
|
|
|
ifp = sc->bfe_ifp;
|
|
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
|
sc->bfe_flags &= ~BFE_FLAG_LINK;
|
|
callout_stop(&sc->bfe_stat_co);
|
|
sc->bfe_watchdog_timer = 0;
|
|
|
|
bfe_chip_halt(sc);
|
|
bfe_tx_ring_free(sc);
|
|
bfe_rx_ring_free(sc);
|
|
}
|