126 lines
4.0 KiB
ArmAsm
126 lines
4.0 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_sa11x0.S,v 1.3 2002/08/17 16:36:32 thorpej Exp $ */
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/*-
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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.data
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.global _C_LABEL(sa11x0_idle_mem)
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_C_LABEL(sa11x0_idle_mem):
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.word 0
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.text
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.align 5
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/* We're now 32-byte aligned */
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.Lsa11x0_idle_mem:
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.word _C_LABEL(sa11x0_idle_mem) /* 1 */
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/*
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* sa11x0_cpusleep
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*
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* This is called when there is nothing on any of the run queues.
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* We go into IDLE mode so that any IRQ or FIQ will awaken us.
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*/
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ENTRY(sa11x0_cpu_sleep)
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ldr r1, .Lsa11x0_idle_mem /* get address of... */ /* 2 */
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nop /* 3 */
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ldr r1, [r1] /* ...non-cacheable page */ /* 4 */
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nop /* 5 */
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/*
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* SA-1110 manual, 9.5.2.1 (Entering Idle Mode) says that
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* to enter idle mode:
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*
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* * Disable clock switching
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* * Issue load from non-cacheable address
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* * Issue "wait for interrupt"
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*
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* The 3-insn sequence must reside in the first 3 words
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* of a cache line.
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*
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* We must disable interrupts in the CPSR so that we can
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* re-enable clock switching before servicing interrupts.
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*/
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mrs r3, cpsr_all /* 6 */
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orr r2, r3, #(I32_bit|F32_bit) /* 7 */
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msr cpsr_all, r2 /* 8 */
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/* We're now 32-byte aligned */
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mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */
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ldr r0, [r1] /* load from non-cacheable address */
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mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt */
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mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */
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/* Restore interrupts (which will cause them to be serviced). */
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msr cpsr_all, r3
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RET
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/*
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* This function is the same as sa110_context_switch for now, the plan
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* is to make use of the process id register to avoid cache flushes.
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*/
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ENTRY(sa11x0_context_switch)
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/*
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* CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
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* Thus the data cache will contain only kernel data and the
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* instruction cache will contain only kernel code, and all
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* kernel mappings are shared by all processes.
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*/
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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/* Make sure that pipeline is emptied */
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mov r0, r0
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mov r0, r0
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RET
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ENTRY(sa11x0_drain_readbuf)
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mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
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RET
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