32a1e9e4a5
rev. 55. The modern CPUs cache and TLB descriptions looked quite questionable without the update, e.g. Haswell i7 4770S reported: Data TLB: 4 KB pages, 4-way set associative, 64 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line After the update, the report is: Data TLB: 1 GByte pages, 4-way set associative, 4 entries Data TLB: 4 KB pages, 4-way set associative, 64 entries Instruction TLB: 2M/4M pages, fully associative, 8 entries Instruction TLB: 4KByte pages, 8-way set associative, 64 entries 64-Byte prefetching Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line Some tags were apparently removed from the table 3-21, Vol. 2A. Keep them around, but add a comment stating the removal. Update the format line for cpu_stdext_feature according to the bits from the SDM rev.55. It appears that Haswells do not store %cs and %ds values in the FPU save area. Store content of the %ecx register from the CPUID leaf 0x7 subleaf 0 as cpu_stdext_feature2 and print defined bits from it, again acording to SDM rev. 55. Sponsored by: The FreeBSD Foundation MFC after: 1 week
223 lines
6.8 KiB
C
223 lines
6.8 KiB
C
/*-
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* Copyright (c) KATO Takenori, 1997, 1998.
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*
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* All rights reserved. Unpublished rights reserved under the copyright
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* laws of Japan.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/pcpu.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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static int hw_instruction_sse;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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&hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
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/*
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* -1: automatic (default)
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* 0: keep enable CLFLUSH
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* 1: force disable CLFLUSH
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*/
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static int hw_clflush_disable = -1;
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int cpu; /* Are we 386, 386sx, 486, etc? */
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u_int cpu_feature; /* Feature flags */
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u_int cpu_feature2; /* Feature flags */
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u_int amd_feature; /* AMD feature flags */
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u_int amd_feature2; /* AMD feature flags */
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u_int amd_pminfo; /* AMD advanced power management info */
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u_int via_feature_rng; /* VIA RNG features */
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u_int via_feature_xcrypt; /* VIA ACE features */
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u_int cpu_high; /* Highest arg to CPUID */
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u_int cpu_exthigh; /* Highest arg to extended CPUID */
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u_int cpu_id; /* Stepping ID */
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u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
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u_int cpu_procinfo2; /* Multicore info */
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char cpu_vendor[20]; /* CPU Origin code */
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u_int cpu_vendor_id; /* CPU vendor ID */
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u_int cpu_fxsr; /* SSE enabled */
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u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
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u_int cpu_clflush_line_size = 32;
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u_int cpu_stdext_feature;
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u_int cpu_stdext_feature2;
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u_int cpu_max_ext_state_size;
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u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
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u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
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u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
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u_int cpu_maxphyaddr; /* Max phys addr width in bits */
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SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
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&via_feature_rng, 0, "VIA RNG feature available in CPU");
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SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
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&via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
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static void
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init_amd(void)
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{
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/*
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* Work around Erratum 721 for Family 10h and 12h processors.
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* These processors may incorrectly update the stack pointer
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* after a long series of push and/or near-call instructions,
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* or a long series of pop and/or near-return instructions.
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*
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* http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
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* http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
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*
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* Hypervisors do not provide access to the errata MSR,
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* causing #GP exception on attempt to apply the errata. The
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* MSR write shall be done on host and persist globally
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* anyway, so do not try to do it when under virtualization.
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*/
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switch (CPUID_TO_FAMILY(cpu_id)) {
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case 0x10:
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case 0x12:
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if ((cpu_feature2 & CPUID2_HV) == 0)
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wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
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break;
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}
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}
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/*
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* Initialize special VIA features
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*/
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static void
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init_via(void)
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{
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u_int regs[4], val;
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/*
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* Check extended CPUID for PadLock features.
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*
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* http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
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*/
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do_cpuid(0xc0000000, regs);
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if (regs[0] >= 0xc0000001) {
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do_cpuid(0xc0000001, regs);
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val = regs[3];
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} else
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return;
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/* Enable RNG if present. */
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if ((val & VIA_CPUID_HAS_RNG) != 0) {
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via_feature_rng = VIA_HAS_RNG;
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wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
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}
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/* Enable PadLock if present. */
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if ((val & VIA_CPUID_HAS_ACE) != 0)
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via_feature_xcrypt |= VIA_HAS_AES;
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if ((val & VIA_CPUID_HAS_ACE2) != 0)
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via_feature_xcrypt |= VIA_HAS_AESCTR;
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if ((val & VIA_CPUID_HAS_PHE) != 0)
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via_feature_xcrypt |= VIA_HAS_SHA;
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if ((val & VIA_CPUID_HAS_PMM) != 0)
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via_feature_xcrypt |= VIA_HAS_MM;
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if (via_feature_xcrypt != 0)
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wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
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}
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/*
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* Initialize CPU control registers
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*/
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void
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initializecpu(void)
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{
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uint64_t msr;
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uint32_t cr4;
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cr4 = rcr4();
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if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
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cr4 |= CR4_FXSR | CR4_XMM;
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cpu_fxsr = hw_instruction_sse = 1;
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}
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if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
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cr4 |= CR4_FSGSBASE;
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/*
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* Postpone enabling the SMEP on the boot CPU until the page
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* tables are switched from the boot loader identity mapping
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* to the kernel tables. The boot loader enables the U bit in
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* its tables.
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*/
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if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
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cr4 |= CR4_SMEP;
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load_cr4(cr4);
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if ((amd_feature & AMDID_NX) != 0) {
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msr = rdmsr(MSR_EFER) | EFER_NXE;
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wrmsr(MSR_EFER, msr);
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pg_nx = PG_NX;
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}
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switch (cpu_vendor_id) {
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case CPU_VENDOR_AMD:
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init_amd();
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break;
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case CPU_VENDOR_CENTAUR:
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init_via();
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break;
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}
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}
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void
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initializecpucache(void)
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{
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/*
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* CPUID with %eax = 1, %ebx returns
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* Bits 15-8: CLFLUSH line size
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* (Value * 8 = cache line size in bytes)
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*/
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if ((cpu_feature & CPUID_CLFSH) != 0)
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cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
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/*
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* XXXKIB: (temporary) hack to work around traps generated
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* when CLFLUSHing APIC register window under virtualization
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* environments. These environments tend to disable the
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* CPUID_SS feature even though the native CPU supports it.
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*/
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TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
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if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
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cpu_feature &= ~CPUID_CLFSH;
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/*
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* Allow to disable CLFLUSH feature manually by
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* hw.clflush_disable tunable.
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*/
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if (hw_clflush_disable == 1)
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cpu_feature &= ~CPUID_CLFSH;
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}
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