4948f4b8d5
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
284 lines
15 KiB
C
284 lines
15 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
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* XAUI.
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*
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* <hr>$Revision: 41586 $<hr>
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*/
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#ifndef __CVMX_HIGIG_H__
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#define __CVMX_HIGIG_H__
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#include "cvmx-wqe.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct
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{
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */
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uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
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DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
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value of b'01' this field should be b'1'. For all other values of HGI it is don't
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care. */
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uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
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SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
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value of b'01' this field should be b'0'. For all other values of HGI it is don't
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care. */
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uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
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to the standard 12-bytes of XGS HiGig header. Each unit represents 4
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bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
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and b'111' are reserved. For HGI field value of b'01' this field should be
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b'01'. For all other values of HGI it is don't care. */
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uint32_t cng_high : 1; /**< Congestion Bit High flag */
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uint32_t hgi : 2; /**< HiGig interface format indicator
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00 = Reserved
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01 = Pure preamble - IEEE standard framing of 10GE
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10 = XGS header - framing based on XGS family definition In this
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format, the default length of the header is 12 bytes and additional
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bytes are indicated by the HDR_EXT_LEN field
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11 = Reserved */
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uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */
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uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */
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} s;
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} dw0;
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet
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000 = Control frames used for CPU to CPU communications
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001 = Unicast packet with destination resolved; The packet can be
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either Layer 2 unicast packet or L3 unicast packet that was
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routed in the ingress chip.
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010 = Broadcast or unknown Unicast packet or unknown multicast,
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destined to all members of the VLAN
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011 = L2 Multicast packet, destined to all ports of the group indicated
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in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
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100 = IP Multicast packet, destined to all ports of the group indicated
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in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
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101 = Reserved
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110 = Reserved
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111 = Reserved */
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uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
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5 is in Byte 9 and bit 6 Is in Byte 1) */
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uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
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on, else it represents the physical port the packet ingressed on. */
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uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
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multicast (unknown L2 multicast and IPMC) packets. This field is used
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when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
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For registered L2 multicast packets:
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PFM= 0 <20> Flood to VLAN
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PFM= 1 or 2 <20> Send to group members in the L2MC table
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For unregistered L2 multicast packets:
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PFM= 0 or 1 <20> Flood to VLAN
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PFM= 2 <20> Drop the packet */
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uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through
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COS_SEL mapping registers to map to the actual MMU queues. */
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uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */
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uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
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uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
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encodings are to make it backward compatible:
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{CNG_HIGH, CNG_LOW] - COLOR
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[0, 0] <20> Packet is green
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[0, 1] <20> Packet is red
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[1, 1] <20> Packet is yellow
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[1, 0] <20> Undefined */
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uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
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00 = Overlay 1 (default)
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01 = Overlay 2 (Classification Tag)
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10 = Reserved
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11 = Reserved */
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} s;
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} dw1;
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
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packet was switched and only needs to be mirrored. */
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uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
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may still need to be switched. */
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uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
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needs to be mirrored. */
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uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
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ingressed the system. */
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uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
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DO_NOT_LEARN bit is overlaid on the second bit of this field. */
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uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
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group. */
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uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
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uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
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added field. */
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uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */
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uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
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is in byte 1) */
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uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in
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byte 1) */
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uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */
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} o1;
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struct
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{
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uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
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uint32_t reserved_0_15 : 16;
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} o2;
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} dw2;
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} cvmx_higig_header_t;
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/**
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* Initialize the HiGig aspects of a XAUI interface. This function
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* should be called before the cvmx-helper generic init.
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*
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* @param interface Interface to initialize HiGig on (0-1)
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* @param enable_higig2
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* Non zero to enable HiGig2 support. Zero to support HiGig
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* and HiGig+.
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*
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* @return Zero on success, negative on failure
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*/
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static inline int cvmx_higig_initialize(int interface, int enable_higig2)
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{
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cvmx_pip_prt_cfgx_t pip_prt_cfg;
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cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp;
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cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt;
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cvmx_gmxx_txx_append_t gmx_tx_append;
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cvmx_gmxx_tx_ifg_t gmx_tx_ifg;
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cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
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cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl;
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cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl;
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int i;
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int header_size = (enable_higig2) ? 16 : 12;
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/* Setup PIP to handle HiGig */
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pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16));
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pip_prt_cfg.s.dsa_en = 0;
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pip_prt_cfg.s.higig_en = 1;
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pip_prt_cfg.s.hg_qos = 1;
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pip_prt_cfg.s.skip = header_size;
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cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64);
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/* Setup some sample QoS defaults. These can be changed later */
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for (i=0; i<64; i++)
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{
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cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
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pip_hg_pri_qos.u64 = 0;
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pip_hg_pri_qos.s.up_qos = 1;
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pip_hg_pri_qos.s.pri = i;
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pip_hg_pri_qos.s.qos = i&7;
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cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
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}
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/* Setup GMX RX to treat the HiGig header as user data to ignore */
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gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface));
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gmx_rx_udd_skp.s.len = header_size;
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gmx_rx_udd_skp.s.fcssel = 0;
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cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64);
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/* Disable GMX preamble checking */
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gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface));
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gmx_rx_frm_ctl.s.pre_chk = 0;
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64);
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/* Setup GMX TX to pad properly min sized packets */
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gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface));
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gmx_tx_min_pkt.s.min_size = 59 + header_size;
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cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64);
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/* Setup GMX TX to not add a preamble */
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gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
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gmx_tx_append.s.preamble = 0;
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cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64);
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/* Reduce the inter frame gap to 8 bytes */
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gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface));
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gmx_tx_ifg.s.ifg1 = 4;
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gmx_tx_ifg.s.ifg2 = 4;
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cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64);
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/* Disable GMX backpressure */
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gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
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gmx_tx_ovr_bp.s.bp = 0;
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gmx_tx_ovr_bp.s.en = 0xf;
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gmx_tx_ovr_bp.s.ign_full = 0xf;
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cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
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if (enable_higig2)
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{
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/* Enable HiGig2 support and forwarding of virtual port backpressure
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to PKO */
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cvmx_gmxx_hg2_control_t gmx_hg2_control;
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gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
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gmx_hg2_control.s.hg2rx_en = 1;
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gmx_hg2_control.s.hg2tx_en = 1;
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gmx_hg2_control.s.logl_en = 0xffff;
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gmx_hg2_control.s.phys_en = 1;
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cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64);
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}
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/* Enable HiGig */
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gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
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gmx_tx_xaui_ctl.s.hg_en = 1;
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cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64);
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif // __CVMX_HIGIG_H__
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