4948f4b8d5
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
529 lines
16 KiB
C
529 lines
16 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the Mips interrupts.
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*
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* <hr>$Revision: 42264 $<hr>
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*/
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#if __GNUC__ >= 4
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/* Backtrace is only available with the new toolchain. */
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#include <execinfo.h>
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#endif
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-interrupt.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-uart.h"
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#include "cvmx-pow.h"
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#include "cvmx-ebt3000.h"
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#include "cvmx-coremask.h"
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#include "cvmx-spinlock.h"
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#include "cvmx-app-init.h"
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EXTERN_ASM void cvmx_interrupt_stage1(void);
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EXTERN_ASM void cvmx_interrupt_cache_error(void);
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/**
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* Internal status the interrupt registration
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*/
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typedef struct
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{
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cvmx_interrupt_func_t handlers[256]; /**< One function to call per interrupt */
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void * data[256]; /**< User data per interrupt */
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cvmx_interrupt_exception_t exception_handler;
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} cvmx_interrupt_state_t;
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/**
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* Internal state the interrupt registration
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*/
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static CVMX_SHARED cvmx_interrupt_state_t cvmx_interrupt_state;
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static CVMX_SHARED cvmx_spinlock_t cvmx_interrupt_default_lock;
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#define COP0_CAUSE "$13,0"
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#define COP0_STATUS "$12,0"
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#define COP0_BADVADDR "$8,0"
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#define COP0_EPC "$14,0"
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#define READ_COP0(dest, R) asm volatile ("dmfc0 %[rt]," R : [rt] "=r" (dest))
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#define ULL unsigned long long
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/**
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* @INTERNAL
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* Dump all useful registers to the console
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*
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* @param registers CPU register to dump
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*/
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static void __cvmx_interrupt_dump_registers(uint64_t registers[32])
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{
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static const char *name[32] = {"r0","at","v0","v1","a0","a1","a2","a3",
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"t0","t1","t2","t3","t4","t5","t6","t7","s0","s1","s2","s3","s4","s5",
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"s6","s7", "t8","t9", "k0","k1","gp","sp","s8","ra"};
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uint64_t reg;
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for (reg=0; reg<16; reg++)
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{
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cvmx_safe_printf("%3s ($%02d): 0x%016llx \t %3s ($%02d): 0x%016llx\n",
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name[reg], (int)reg, (ULL)registers[reg], name[reg+16], (int)reg+16, (ULL)registers[reg+16]);
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}
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READ_COP0(reg, COP0_CAUSE);
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cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_CAUSE", (ULL)reg);
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READ_COP0(reg, COP0_STATUS);
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cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_STATUS", (ULL)reg);
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READ_COP0(reg, COP0_BADVADDR);
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cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_BADVADDR", (ULL)reg);
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READ_COP0(reg, COP0_EPC);
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cvmx_safe_printf("%16s: 0x%016llx\n", "COP0_EPC", (ULL)reg);
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}
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/**
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* @INTERNAL
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* Default exception handler. Prints out the exception
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* cause decode and all relevant registers.
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*
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* @param registers Registers at time of the exception
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*/
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static void __cvmx_interrupt_default_exception_handler(uint64_t registers[32])
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{
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uint64_t trap_print_cause;
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ebt3000_str_write("Trap");
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cvmx_spinlock_lock(&cvmx_interrupt_default_lock);
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cvmx_safe_printf("******************************************************************\n");
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cvmx_safe_printf("Core %d: Unhandled Exception. Cause register decodes to:\n", (int)cvmx_get_core_num());
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READ_COP0(trap_print_cause, COP0_CAUSE);
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switch ((trap_print_cause >> 2) & 0x1f)
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{
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case 0x0:
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cvmx_safe_printf("Interrupt\n");
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break;
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case 0x1:
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cvmx_safe_printf("TLB Mod\n");
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break;
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case 0x2:
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cvmx_safe_printf("tlb load/fetch\n");
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break;
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case 0x3:
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cvmx_safe_printf("tlb store\n");
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break;
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case 0x4:
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cvmx_safe_printf("address exc, load/fetch\n");
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break;
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case 0x5:
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cvmx_safe_printf("address exc, store\n");
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break;
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case 0x6:
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cvmx_safe_printf("bus error, inst. fetch\n");
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break;
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case 0x7:
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cvmx_safe_printf("bus error, load/store\n");
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break;
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case 0x8:
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cvmx_safe_printf("syscall\n");
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break;
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case 0x9:
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cvmx_safe_printf("breakpoint \n");
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break;
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case 0xa:
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cvmx_safe_printf("reserved instruction\n");
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break;
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case 0xb:
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cvmx_safe_printf("cop unusable\n");
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break;
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case 0xc:
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cvmx_safe_printf("arithmetic overflow\n");
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break;
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case 0xd:
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cvmx_safe_printf("trap\n");
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break;
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case 0xf:
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cvmx_safe_printf("floating point exc\n");
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break;
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case 0x12:
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cvmx_safe_printf("cop2 exception\n");
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break;
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case 0x16:
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cvmx_safe_printf("mdmx unusable\n");
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break;
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case 0x17:
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cvmx_safe_printf("watch\n");
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break;
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case 0x18:
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cvmx_safe_printf("machine check\n");
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break;
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case 0x1e:
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cvmx_safe_printf("cache error\n");
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break;
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default:
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cvmx_safe_printf("Reserved exception cause.\n");
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break;
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}
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cvmx_safe_printf("******************************************************************\n");
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__cvmx_interrupt_dump_registers(registers);
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cvmx_safe_printf("******************************************************************\n");
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#if __GNUC__ >= 4 && !defined(OCTEON_DISABLE_BACKTRACE)
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cvmx_safe_printf("Backtrace:\n\n");
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__octeon_print_backtrace_func ((__octeon_backtrace_printf_t)cvmx_safe_printf);
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cvmx_safe_printf("******************************************************************\n");
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#endif
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cvmx_spinlock_unlock(&cvmx_interrupt_default_lock);
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if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
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CVMX_BREAK;
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while (1)
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{
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/* Interrupts are suppressed when we are in the exception
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handler (because of SR[EXL]). Spin and poll the uart
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status and see if the debugger is trying to stop us. */
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cvmx_uart_lsr_t lsrval;
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lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(cvmx_debug_uart));
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if (lsrval.s.dr)
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{
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uint64_t tmp;
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/* Pulse the MCD0 signal. */
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asm volatile (
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".set push\n"
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".set noreorder\n"
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".set mips64\n"
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"dmfc0 %0, $22\n"
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"ori %0, %0, 0x10\n"
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"dmtc0 %0, $22\n"
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".set pop\n"
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: "=r" (tmp));
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}
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}
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}
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/**
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* @INTERNAL
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* Default interrupt handler if the user doesn't register one.
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*
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* @param irq_number IRQ that caused this interrupt
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* @param registers Register at the time of the interrupt
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* @param user_arg Unused optional user data
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*/
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static void __cvmx_interrupt_default(int irq_number, uint64_t registers[32], void *user_arg)
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{
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cvmx_safe_printf("cvmx_interrupt_default: Received interrupt %d\n", irq_number);
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__cvmx_interrupt_dump_registers(registers);
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}
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/**
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* @INTERNAL
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* Handler for interrupt lines 2 and 3. These are directly tied
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* to the CIU. The handler queres the status of the CIU and
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* calls the secondary handler for the CIU interrupt that
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* occurred.
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*
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* @param irq_number Interrupt number that fired (2 or 3)
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* @param registers Registers at the time of the interrupt
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* @param user_arg Unused user argument
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*/
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static void __cvmx_interrupt_ciu(int irq_number, uint64_t registers[32], void *user_arg)
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{
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int ciu_offset = cvmx_get_core_num() * 2 + irq_number - 2;
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uint64_t irq_mask = cvmx_read_csr(CVMX_CIU_INTX_SUM0(ciu_offset)) & cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
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int irq = 8;
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/* Handle EN0 sources */
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while (irq_mask)
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{
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if (irq_mask&1)
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{
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cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
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return;
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}
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irq_mask = irq_mask >> 1;
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irq++;
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}
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/* Handle EN1 sources */
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irq_mask = cvmx_read_csr(CVMX_CIU_INT_SUM1) & cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
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irq = 8 + 64;
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while (irq_mask)
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{
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if (irq_mask&1)
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{
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cvmx_interrupt_state.handlers[irq](irq, registers, cvmx_interrupt_state.data[irq]);
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return;
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}
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irq_mask = irq_mask >> 1;
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irq++;
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}
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}
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/**
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* @INTERNAL
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* Called for all RML interrupts. This is usually an ECC error
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*
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* @param irq_number Interrupt number that we're being called for
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* @param registers Registers at the time of the interrupt
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* @param user_arg Unused user argument
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*/
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static void __cvmx_interrupt_ecc(int irq_number, uint64_t registers[32], void *user_arg)
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{
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cvmx_interrupt_rsl_decode();
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}
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/**
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* Process an interrupt request
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*
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* @param registers Registers at time of interrupt / exception
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* Registers 0-31 are standard MIPS, others specific to this routine
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* @return
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*/
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EXTERN_ASM void cvmx_interrupt_do_irq(uint64_t registers[35]);
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void cvmx_interrupt_do_irq(uint64_t registers[35])
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{
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uint64_t mask;
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uint64_t cause;
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uint64_t status;
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uint64_t cache_err;
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int i;
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uint32_t exc_vec;
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/* Determine the cause of the interrupt */
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asm volatile ("dmfc0 %0,$13,0" : "=r" (cause));
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asm volatile ("dmfc0 %0,$12,0" : "=r" (status));
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/* The assembly stub at each exception vector saves its address in k1 when
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** it calls the stage 2 handler. We use this to compute the exception vector
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** that brought us here */
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exc_vec = (uint32_t)(registers[27] & 0x780); /* Mask off bits we need to ignore */
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/* Check for cache errors. The cache errors go to a separate exception vector,
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** so we will only check these if we got here from a cache error exception, and
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** the ERL (error level) bit is set. */
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if (exc_vec == 0x100 && (status & 0x4))
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{
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i = cvmx_get_core_num();
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CVMX_MF_CACHE_ERR(cache_err);
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/* Use copy of DCACHE_ERR register that early exception stub read */
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if (registers[34] & 0x1)
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{
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cvmx_safe_printf("Dcache error detected: core: %d, set: %d, va 6:3: 0x%x\n", i, (int)(cache_err >> 3) & 0x3, (int)(cache_err >> 3) & 0xf);
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uint64_t dcache_err = 0;
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CVMX_MT_DCACHE_ERR(dcache_err);
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}
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else if (cache_err & 0x1)
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{
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cvmx_safe_printf("Icache error detected: core: %d, set: %d, way : %d\n", i, (int)(cache_err >> 5) & 0x3f, (int)(cache_err >> 7) & 0x3);
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cache_err = 0;
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CVMX_MT_CACHE_ERR(cache_err);
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}
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else
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cvmx_safe_printf("Cache error exception: core %d\n", i);
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}
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if ((cause & 0x7c) != 0)
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{
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cvmx_interrupt_state.exception_handler(registers);
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return;
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}
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/* Convert the cause into an active mask */
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mask = ((cause & status) >> 8) & 0xff;
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if (mask == 0)
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return; /* Spurious interrupt */
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for (i=0; i<8; i++)
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{
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if (mask & (1<<i))
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{
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cvmx_interrupt_state.handlers[i](i, registers, cvmx_interrupt_state.data[i]);
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return;
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}
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}
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/* We should never get here */
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__cvmx_interrupt_default_exception_handler(registers);
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}
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/**
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* Initialize the interrupt routine and copy the low level
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* stub into the correct interrupt vector. This is called
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* automatically during application startup.
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*/
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void cvmx_interrupt_initialize(void)
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{
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void *low_level_loc;
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cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
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int i;
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/* Disable all CIU interrupts by default */
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cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
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cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
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if (cvmx_coremask_first_core(sys_info_ptr->core_mask))
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{
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cvmx_interrupt_state.exception_handler = __cvmx_interrupt_default_exception_handler;
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for (i=0; i<256; i++)
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{
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cvmx_interrupt_state.handlers[i] = __cvmx_interrupt_default;
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cvmx_interrupt_state.data[i] = NULL;
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}
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low_level_loc = CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,sys_info_ptr->exception_base_addr));
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memcpy(low_level_loc + 0x80, (void*)cvmx_interrupt_stage1, 0x80);
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memcpy(low_level_loc + 0x100, (void*)cvmx_interrupt_cache_error, 0x80);
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memcpy(low_level_loc + 0x180, (void*)cvmx_interrupt_stage1, 0x80);
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memcpy(low_level_loc + 0x200, (void*)cvmx_interrupt_stage1, 0x80);
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/* Make sure the locations used to count Icache and Dcache exceptions
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starts out as zero */
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cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 8), 0);
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cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 16), 0);
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cvmx_write64_uint64(CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, 24), 0);
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CVMX_SYNC;
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/* Add an interrupt handlers for chained CIU interrupts */
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cvmx_interrupt_register(CVMX_IRQ_CIU0, __cvmx_interrupt_ciu, NULL);
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cvmx_interrupt_register(CVMX_IRQ_CIU1, __cvmx_interrupt_ciu, NULL);
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/* Add an interrupt handler for ECC failures */
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cvmx_interrupt_register(CVMX_IRQ_RML, __cvmx_interrupt_ecc, NULL);
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cvmx_interrupt_rsl_enable();
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cvmx_interrupt_unmask_irq(CVMX_IRQ_RML);
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}
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cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU0);
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cvmx_interrupt_unmask_irq(CVMX_IRQ_CIU1);
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CVMX_ICACHE_INVALIDATE;
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/* Enable interrupts for each core (bit0 of COP0 Status) */
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uint32_t mask;
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asm volatile (
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"mfc0 %0,$12,0\n"
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"ori %0, %0, 1\n"
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"mtc0 %0,$12,0\n"
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: "=r" (mask));
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}
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/**
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* Register an interrupt handler for the specified interrupt number.
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*
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* @param irq_number Interrupt number to register for (0-135) See
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* cvmx-interrupt.h for enumeration and description of sources.
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* @param func Function to call on interrupt.
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* @param user_arg User data to pass to the interrupt handler
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*/
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void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg)
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{
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cvmx_interrupt_state.handlers[irq_number] = func;
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cvmx_interrupt_state.data[irq_number] = user_arg;
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CVMX_SYNCWS;
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}
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/**
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* Set the exception handler for all non interrupt sources.
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*
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* @param handler New exception handler
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* @return Old exception handler
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*/
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cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler)
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{
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cvmx_interrupt_exception_t result = cvmx_interrupt_state.exception_handler;
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cvmx_interrupt_state.exception_handler = handler;
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|
CVMX_SYNCWS;
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return result;
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|
}
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|
|
|
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/**
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* version of printf that works better in exception context.
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|
*
|
|
* @param format
|
|
*/
|
|
void cvmx_safe_printf(const char *format, ...)
|
|
{
|
|
static char buffer[256];
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|
va_list args;
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|
va_start(args, format);
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|
int count = vsnprintf(buffer, sizeof(buffer), format, args);
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|
va_end(args);
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|
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|
char *ptr = buffer;
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while (count-- > 0)
|
|
{
|
|
cvmx_uart_lsr_t lsrval;
|
|
|
|
/* Spin until there is room */
|
|
do
|
|
{
|
|
lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
|
|
if (lsrval.s.temt == 0)
|
|
cvmx_wait(10000); /* Just to reduce the load on the system */
|
|
}
|
|
while (lsrval.s.temt == 0);
|
|
|
|
if (*ptr == '\n')
|
|
cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
|
|
cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
|
|
}
|
|
}
|
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