297 lines
7.5 KiB
C
297 lines
7.5 KiB
C
/*-
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* Copyright (c) 2007 Sepherosa Ziehau. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Sepherosa Ziehau <sepherosa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $
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* $FreeBSD$
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*/
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#ifndef _IF_ETVAR_H
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#define _IF_ETVAR_H
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/* DragonFly compatibility */
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#define EVL_ENCAPLEN ETHER_VLAN_ENCAP_LEN
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/*
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* Allocate the right type of mbuf for the desired total length.
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*/
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static __inline struct mbuf *
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m_getl(int len, int how, int type, int flags, int *psize)
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{
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struct mbuf *m;
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int size;
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if (len >= MINCLSIZE) {
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m = m_getcl(how, type, flags);
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size = MCLBYTES;
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} else if (flags & M_PKTHDR) {
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m = m_gethdr(how, type);
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size = MHLEN;
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} else {
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m = m_get(how, type);
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size = MLEN;
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}
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if (psize != NULL)
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*psize = size;
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return (m);
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}
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#define ET_ALIGN 0x1000
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#define ET_NSEG_MAX 32 /* XXX no limit actually */
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#define ET_NSEG_SPARE 8
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#define ET_TX_NDESC 512
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#define ET_RX_NDESC 512
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#define ET_RX_NRING 2
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#define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC)
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#define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc))
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#define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc))
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#define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat))
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#define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \
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ET_MEM_TXSIZE_EX)
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#define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \
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EVL_ENCAPLEN - ETHER_CRC_LEN)
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#define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \
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ETHER_CRC_LEN)
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#define ET_JSLOTS (ET_RX_NDESC + 128)
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#define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN)
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#define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN)
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#define CSR_WRITE_4(sc, reg, val) \
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bus_write_4((sc)->sc_mem_res, (reg), (val))
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#define CSR_READ_4(sc, reg) \
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bus_read_4((sc)->sc_mem_res, (reg))
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#define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32)
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#define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff)
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struct et_txdesc {
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uint32_t td_addr_hi;
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uint32_t td_addr_lo;
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uint32_t td_ctrl1; /* ET_TDCTRL1_ */
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uint32_t td_ctrl2; /* ET_TDCTRL2_ */
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};
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#define ET_TDCTRL1_LEN_MASK 0x0000FFFF
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#define ET_TDCTRL2_LAST_FRAG 0x00000001
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#define ET_TDCTRL2_FIRST_FRAG 0x00000002
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#define ET_TDCTRL2_INTR 0x00000004
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#define ET_TDCTRL2_CTRL_WORD 0x00000008
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#define ET_TDCTRL2_HDX_BACKP 0x00000010
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#define ET_TDCTRL2_XMIT_PAUSE 0x00000020
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#define ET_TDCTRL2_FRAME_ERR 0x00000040
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#define ET_TDCTRL2_NO_CRC 0x00000080
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#define ET_TDCTRL2_MAC_OVRRD 0x00000100
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#define ET_TDCTRL2_PAD_PACKET 0x00000200
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#define ET_TDCTRL2_JUMBO_PACKET 0x00000400
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#define ET_TDCTRL2_INS_VLAN 0x00000800
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#define ET_TDCTRL2_CSUM_IP 0x00001000
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#define ET_TDCTRL2_CSUM_TCP 0x00002000
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#define ET_TDCTRL2_CSUM_UDP 0x00004000
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struct et_rxdesc {
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uint32_t rd_addr_lo;
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uint32_t rd_addr_hi;
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uint32_t rd_ctrl; /* ET_RDCTRL_ */
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};
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#define ET_RDCTRL_BUFIDX_MASK 0x000003FF
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struct et_rxstat {
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uint32_t rxst_info1;
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uint32_t rxst_info2; /* ET_RXST_INFO2_ */
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};
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#define ET_RXST_INFO2_LEN_MASK 0x0000FFFF
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#define ET_RXST_INFO2_LEN_SHIFT 0
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#define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000
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#define ET_RXST_INFO2_BUFIDX_SHIFT 16
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#define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000
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#define ET_RXST_INFO2_RINGIDX_SHIFT 26
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struct et_rxstatus {
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uint32_t rxs_ring;
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uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */
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};
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#define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000
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#define ET_RXS_STATRING_INDEX_SHIFT 16
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#define ET_RXS_STATRING_WRAP 0x10000000
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struct et_dmamap_ctx {
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int nsegs;
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bus_dma_segment_t *segs;
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};
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struct et_txbuf {
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struct mbuf *tb_mbuf;
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bus_dmamap_t tb_dmap;
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};
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struct et_rxbuf {
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struct mbuf *rb_mbuf;
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bus_dmamap_t rb_dmap;
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bus_addr_t rb_paddr;
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};
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struct et_txstatus_data {
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uint32_t *txsd_status;
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bus_addr_t txsd_paddr;
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bus_dma_tag_t txsd_dtag;
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bus_dmamap_t txsd_dmap;
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};
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struct et_rxstatus_data {
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struct et_rxstatus *rxsd_status;
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bus_addr_t rxsd_paddr;
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bus_dma_tag_t rxsd_dtag;
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bus_dmamap_t rxsd_dmap;
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};
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struct et_rxstat_ring {
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struct et_rxstat *rsr_stat;
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bus_addr_t rsr_paddr;
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bus_dma_tag_t rsr_dtag;
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bus_dmamap_t rsr_dmap;
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int rsr_index;
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int rsr_wrap;
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};
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struct et_txdesc_ring {
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struct et_txdesc *tr_desc;
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bus_addr_t tr_paddr;
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bus_dma_tag_t tr_dtag;
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bus_dmamap_t tr_dmap;
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int tr_ready_index;
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int tr_ready_wrap;
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};
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struct et_rxdesc_ring {
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struct et_rxdesc *rr_desc;
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bus_addr_t rr_paddr;
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bus_dma_tag_t rr_dtag;
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bus_dmamap_t rr_dmap;
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uint32_t rr_posreg;
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int rr_index;
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int rr_wrap;
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};
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struct et_txbuf_data {
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struct et_txbuf tbd_buf[ET_TX_NDESC];
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int tbd_start_index;
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int tbd_start_wrap;
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int tbd_used;
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};
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struct et_softc;
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struct et_rxbuf_data;
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typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int);
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struct et_rxbuf_data {
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struct et_rxbuf rbd_buf[ET_RX_NDESC];
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struct et_softc *rbd_softc;
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struct et_rxdesc_ring *rbd_ring;
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int rbd_bufsize;
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et_newbuf_t rbd_newbuf;
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};
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struct et_softc {
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struct ifnet *ifp;
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device_t dev;
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struct mtx sc_mtx;
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device_t sc_miibus;
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void *sc_irq_handle;
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struct resource *sc_irq_res;
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struct resource *sc_mem_res;
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struct arpcom arpcom;
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int sc_if_flags;
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uint32_t sc_flags; /* ET_FLAG_ */
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int sc_expcap;
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int sc_mem_rid;
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int sc_irq_rid;
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struct callout sc_tick;
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int watchdog_timer;
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bus_dma_tag_t sc_dtag;
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struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING];
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struct et_rxstat_ring sc_rxstat_ring;
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struct et_rxstatus_data sc_rx_status;
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struct et_txdesc_ring sc_tx_ring;
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struct et_txstatus_data sc_tx_status;
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bus_dma_tag_t sc_mbuf_dtag;
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bus_dmamap_t sc_mbuf_tmp_dmap;
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struct et_rxbuf_data sc_rx_data[ET_RX_NRING];
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struct et_txbuf_data sc_tx_data;
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uint32_t sc_tx;
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uint32_t sc_tx_intr;
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/*
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* Sysctl variables
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*/
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int sc_rx_intr_npkts;
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int sc_rx_intr_delay;
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int sc_tx_intr_nsegs;
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uint32_t sc_timer;
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};
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#define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define ET_FLAG_PCIE 0x0001
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#define ET_FLAG_MSI 0x0002
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#define ET_FLAG_TXRX_ENABLED 0x0100
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#define ET_FLAG_JUMBO 0x0200
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#endif /* !_IF_ETVAR_H */
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