jhibbits 4c38c193d4 Disable interrupts when updating the TLB
Without disabling interrupts it's possible for another thread to preempt
and update the registers post-read (tlb1_read_entry) or pre-write
(tlb1_write_entry), and confuse the kernel with mixed register states.

MFC after:	2 weeks
2017-06-27 01:57:22 +00:00
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