1f77f137dc
PR: 191174 Submitted by: Franco Fichtner <franco at lastsummer.de>
881 lines
38 KiB
Groff
881 lines
38 KiB
Groff
.\" Copyright (c) 2010 Fabien Thomas. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 24, 2010
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.Dt PMC.COREI7UC 3
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.Os
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.Sh NAME
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.Nm pmc.corei7uc
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.Nd uncore measurement events for
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.Tn Intel
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.Tn Core i7 and Xeon 5500
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Core i7"
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CPUs contain PMCs conforming to version 2 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs contain 2 classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_UCP"
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.It Li PMC_CLASS_UCF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_UCP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Core i7 and Xeon 5500 PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
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.%T "Volume 3B: System Programming Guide, Part 2"
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.%N "Order Number: 253669-033US"
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.%D December 2009
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.%Q "Intel Corporation"
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.Re
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.Ss COREI7 AND XEON 5500 UNCORE FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.ucf 3 .
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.Ss COREI7 AND XEON 5500 UNCORE PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta \&No
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta \&No
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta \&No
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.El
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.Ss Event Specifiers (Programmable PMCs)
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Core i7 and Xeon 5500 uncore programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li GQ_CYCLES_FULL.READ_TRACKER
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.Pq Event 00H , Umask 01H
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Uncore cycles Global Queue read tracker is full.
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.It Li GQ_CYCLES_FULL.WRITE_TRACKER
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.Pq Event 00H , Umask 02H
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Uncore cycles Global Queue write tracker is full.
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.It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER
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.Pq Event 00H , Umask 04H
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Uncore cycles Global Queue peer probe tracker is full. The peer probe
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tracker queue tracks snoops from the IOH and remote sockets.
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.It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER
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.Pq Event 01H , Umask 01H
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Uncore cycles were Global Queue read tracker has at least one valid entry.
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.It Li GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER
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.Pq Event 01H , Umask 02H
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Uncore cycles were Global Queue write tracker has at least one valid entry.
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.It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER
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.Pq Event 01H , Umask 04H
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Uncore cycles were Global Queue peer probe tracker has at least one valid
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entry. The peer probe tracker queue tracks IOH and remote socket snoops.
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.It Li GQ_ALLOC.READ_TRACKER
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.Pq Event 03H , Umask 01H
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Counts the number of tread tracker allocate to deallocate entries. The GQ
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read tracker allocate to deallocate occupancy count is divided by the count
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to obtain the average read tracker latency.
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.It Li GQ_ALLOC.RT_L3_MISS
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.Pq Event 03H , Umask 02H
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Counts the number GQ read tracker entries for which a full cache line read
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has missed the L3. The GQ read tracker L3 miss to fill occupancy count is
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divided by this count to obtain the average cache line read L3 miss latency.
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The latency represents the time after which the L3 has determined that the
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cache line has missed. The time between a GQ read tracker allocation and the
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L3 determining that the cache line has missed is the average L3 hit latency.
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The total L3 cache line read miss latency is the hit latency + L3 miss
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latency.
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.It Li GQ_ALLOC.RT_TO_L3_RESP
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.Pq Event 03H , Umask 04H
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Counts the number of GQ read tracker entries that are allocated in the read
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tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy
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count is divided by this count to obtain the average L3 hit latency.
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.It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED
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.Pq Event 03H , Umask 08H
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Counts the number of GQ read tracker entries that are allocated in the read
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tracker, have missed in the L3 and have not acquired a Request Transaction
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ID. The GQ read tracker L3 miss to RTID acquired occupancy count is
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divided by this count to obtain the average latency for a read L3 miss to
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acquire an RTID.
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.It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED
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.Pq Event 03H , Umask 10H
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Counts the number of GQ write tracker entries that are allocated in the
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write tracker, have missed in the L3 and have not acquired a Request
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Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is
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divided by this count to obtain the average latency for a write L3 miss to
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acquire an RTID.
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.It Li GQ_ALLOC.WRITE_TRACKER
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.Pq Event 03H , Umask 20H
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Counts the number of GQ write tracker entries that are allocated in the
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write tracker queue that miss the L3. The GQ write tracker occupancy count
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is divided by the this count to obtain the average L3 write miss latency.
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.It Li GQ_ALLOC.PEER_PROBE_TRACKER
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.Pq Event 03H , Umask 40H
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Counts the number of GQ peer probe tracker (snoop) entries that are
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allocated in the peer probe tracker queue that miss the L3. The GQ peer
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probe occupancy count is divided by this count to obtain the average L3 peer
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probe miss latency.
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.It Li GQ_DATA.FROM_QPI
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.Pq Event 04H , Umask 01H
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Cycles Global Queue Quickpath Interface input data port is busy importing
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data from the Quickpath Interface. Each cycle the input port can transfer 8
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or 16 bytes of data.
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.It Li GQ_DATA.FROM_QMC
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.Pq Event 04H , Umask 02H
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Cycles Global Queue Quickpath Memory Interface input data port is busy
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importing data from the Quickpath Memory Interface. Each cycle the input
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port can transfer 8 or 16 bytes of data.
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.It Li GQ_DATA.FROM_L3
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.Pq Event 04H , Umask 04H
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Cycles GQ L3 input data port is busy importing data from the Last Level
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Cache. Each cycle the input port can transfer 32 bytes of data.
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.It Li GQ_DATA.FROM_CORES_02
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.Pq Event 04H , Umask 08H
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Cycles GQ Core 0 and 2 input data port is busy importing data from processor
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cores 0 and 2. Each cycle the input port can transfer 32 bytes of data.
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.It Li GQ_DATA.FROM_CORES_13
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.Pq Event 04H , Umask 10H
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Cycles GQ Core 1 and 3 input data port is busy importing data from processor
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cores 1 and 3. Each cycle the input port can transfer 32 bytes of data.
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.It Li GQ_DATA.TO_QPI_QMC
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.Pq Event 05H , Umask 01H
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Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath
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Interface or Quickpath Memory Interface. Each cycle the output port can
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transfer 32 bytes of data.
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.It Li GQ_DATA.TO_L3
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.Pq Event 05H , Umask 02H
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Cycles GQ L3 output data port is busy sending data to the Last Level Cache.
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Each cycle the output port can transfer 32 bytes of data.
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.It Li GQ_DATA.TO_CORES
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.Pq Event 05H , Umask 04H
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Cycles GQ Core output data port is busy sending data to the Cores. Each
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cycle the output port can transfer 32 bytes of data.
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.It Li SNP_RESP_TO_LOCAL_HOME.I_STATE
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.Pq Event 06H , Umask 01H
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Number of snoop responses to the local home that L3 does not have the
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referenced cache line.
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.It Li SNP_RESP_TO_LOCAL_HOME.S_STATE
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.Pq Event 06H , Umask 02H
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Number of snoop responses to the local home that L3 has the referenced line
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cached in the S state.
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.It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE
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.Pq Event 06H , Umask 04H
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Number of responses to code or data read snoops to the local home that the
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L3 has the referenced cache line in the E state. The L3 cache line state is
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changed to the S state and the line is forwarded to the local home in the S
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state.
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.It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE
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.Pq Event 06H , Umask 08H
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Number of responses to read invalidate snoops to the local home that the L3
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has the referenced cache line in the M state. The L3 cache line state is
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invalidated and the line is forwarded to the local home in the M state.
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.It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT
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.Pq Event 06H , Umask 10H
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Number of conflict snoop responses sent to the local home.
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.It Li SNP_RESP_TO_LOCAL_HOME.WB
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.Pq Event 06H , Umask 20H
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Number of responses to code or data read snoops to the local home that the
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L3 has the referenced line cached in the M state.
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.It Li SNP_RESP_TO_REMOTE_HOME.I_STATE
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.Pq Event 07H , Umask 01H
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Number of snoop responses to a remote home that L3 does not have the
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referenced cache line.
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.It Li SNP_RESP_TO_REMOTE_HOME.S_STATE
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.Pq Event 07H , Umask 02H
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Number of snoop responses to a remote home that L3 has the referenced line
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cached in the S state.
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.It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE
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.Pq Event 07H , Umask 04H
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Number of responses to code or data read snoops to a remote home that the L3
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has the referenced cache line in the E state. The L3 cache line state is
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changed to the S state and the line is forwarded to the remote home in the S
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state.
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.It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE
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.Pq Event 07H , Umask 08H
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Number of responses to read invalidate snoops to a remote home that the L3
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has the referenced cache line in the M state. The L3 cache line state is
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invalidated and the line is forwarded to the remote home in the M state.
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.It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT
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.Pq Event 07H , Umask 10H
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Number of conflict snoop responses sent to the local home.
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.It Li SNP_RESP_TO_REMOTE_HOME.WB
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.Pq Event 07H , Umask 20H
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Number of responses to code or data read snoops to a remote home that the L3
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has the referenced line cached in the M state.
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.It Li SNP_RESP_TO_REMOTE_HOME.HITM
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.Pq Event 07H , Umask 24H
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Number of HITM snoop responses to a remote home
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.It Li L3_HITS.READ
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.Pq Event 08H , Umask 01H
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Number of code read, data read and RFO requests that hit in the L3
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.It Li L3_HITS.WRITE
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.Pq Event 08H , Umask 02H
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Number of writeback requests that hit in the L3. Writebacks from the cores
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will always result in L3 hits due to the inclusive property of the L3.
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.It Li L3_HITS.PROBE
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.Pq Event 08H , Umask 04H
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Number of snoops from IOH or remote sockets that hit in the L3.
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.It Li L3_HITS.ANY
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.Pq Event 08H , Umask 03H
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Number of reads and writes that hit the L3.
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.It Li L3_MISS.READ
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.Pq Event 09H , Umask 01H
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Number of code read, data read and RFO requests that miss the L3.
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.It Li L3_MISS.WRITE
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.Pq Event 09H , Umask 02H
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Number of writeback requests that miss the L3. Should always be zero as
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writebacks from the cores will always result in L3 hits due to the inclusive
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property of the L3.
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.It Li L3_MISS.PROBE
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.Pq Event 09H , Umask 04H
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Number of snoops from IOH or remote sockets that miss the L3.
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.It Li L3_MISS.ANY
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.Pq Event 09H , Umask 03H
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Number of reads and writes that miss the L3.
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.It Li L3_LINES_IN.M_STATE
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.Pq Event 0AH , Umask 01H
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Counts the number of L3 lines allocated in M state. The only time a cache
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line is allocated in the M state is when the line was forwarded in M state
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is forwarded due to a Snoop Read Invalidate Own request.
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.It Li L3_LINES_IN.E_STATE
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.Pq Event 0AH , Umask 02H
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Counts the number of L3 lines allocated in E state.
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.It Li L3_LINES_IN.S_STATE
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.Pq Event 0AH , Umask 04H
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Counts the number of L3 lines allocated in S state.
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.It Li L3_LINES_IN.F_STATE
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.Pq Event 0AH , Umask 08H
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Counts the number of L3 lines allocated in F state.
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.It Li L3_LINES_IN.ANY
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.Pq Event 0AH , Umask 0FH
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Counts the number of L3 lines allocated in any state.
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.It Li L3_LINES_OUT.M_STATE
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.Pq Event 0BH , Umask 01H
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Counts the number of L3 lines victimized that were in the M state. When the
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victim cache line is in M state, the line is written to its home cache agent
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which can be either local or remote.
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.It Li L3_LINES_OUT.E_STATE
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.Pq Event 0BH , Umask 02H
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Counts the number of L3 lines victimized that were in the E state.
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.It Li L3_LINES_OUT.S_STATE
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.Pq Event 0BH , Umask 04H
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Counts the number of L3 lines victimized that were in the S state.
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.It Li L3_LINES_OUT.I_STATE
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.Pq Event 0BH , Umask 08H
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Counts the number of L3 lines victimized that were in the I state.
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.It Li L3_LINES_OUT.F_STATE
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.Pq Event 0BH , Umask 10H
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Counts the number of L3 lines victimized that were in the F state.
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.It Li L3_LINES_OUT.ANY
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.Pq Event 0BH , Umask 1FH
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Counts the number of L3 lines victimized in any state.
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.It Li QHL_REQUESTS.IOH_READS
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.Pq Event 20H , Umask 01H
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Counts number of Quickpath Home Logic read requests from the IOH.
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.It Li QHL_REQUESTS.IOH_WRITES
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.Pq Event 20H , Umask 02H
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Counts number of Quickpath Home Logic write requests from the IOH.
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.It Li QHL_REQUESTS.REMOTE_READS
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.Pq Event 20H , Umask 04H
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Counts number of Quickpath Home Logic read requests from a remote socket.
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.It Li QHL_REQUESTS.REMOTE_WRITES
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.Pq Event 20H , Umask 08H
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Counts number of Quickpath Home Logic write requests from a remote socket.
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.It Li QHL_REQUESTS.LOCAL_READS
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.Pq Event 20H , Umask 10H
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Counts number of Quickpath Home Logic read requests from the local socket.
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.It Li QHL_REQUESTS.LOCAL_WRITES
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.Pq Event 20H , Umask 20H
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Counts number of Quickpath Home Logic write requests from the local socket.
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.It Li QHL_CYCLES_FULL.IOH
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.Pq Event 21H , Umask 01H
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Counts uclk cycles all entries in the Quickpath Home Logic IOH are full.
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.It Li QHL_CYCLES_FULL.REMOTE
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.Pq Event 21H , Umask 02H
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Counts uclk cycles all entries in the Quickpath Home Logic remote tracker
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are full.
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.It Li QHL_CYCLES_FULL.LOCAL
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.Pq Event 21H , Umask 04H
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Counts uclk cycles all entries in the Quickpath Home Logic local tracker are
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full.
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.It Li QHL_CYCLES_NOT_EMPTY.IOH
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.Pq Event 22H , Umask 01H
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Counts uclk cycles all entries in the Quickpath Home Logic IOH is busy.
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.It Li QHL_CYCLES_NOT_EMPTY.REMOTE
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.Pq Event 22H , Umask 02H
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Counts uclk cycles all entries in the Quickpath Home Logic remote tracker is
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busy.
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.It Li QHL_CYCLES_NOT_EMPTY.LOCAL
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.Pq Event 22H , Umask 04H
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Counts uclk cycles all entries in the Quickpath Home Logic local tracker is
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busy.
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.It Li QHL_OCCUPANCY.IOH
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.Pq Event 23H , Umask 01H
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QHL IOH tracker allocate to deallocate read occupancy.
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.It Li QHL_OCCUPANCY.REMOTE
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.Pq Event 23H , Umask 02H
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QHL remote tracker allocate to deallocate read occupancy.
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.It Li QHL_OCCUPANCY.LOCAL
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.Pq Event 23H , Umask 04H
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QHL local tracker allocate to deallocate read occupancy.
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.It Li QHL_ADDRESS_CONFLICTS.2WAY
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.Pq Event 24H , Umask 02H
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Counts number of QHL Active Address Table (AAT) entries that saw a max of 2
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conflicts. The AAT is a structure that tracks requests that are in conflict.
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The requests themselves are in the home tracker entries. The count is
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reported when an AAT entry deallocates.
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.It Li QHL_ADDRESS_CONFLICTS.3WAY
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.Pq Event 24H , Umask 04H
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Counts number of QHL Active Address Table (AAT) entries that saw a max of 3
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conflicts. The AAT is a structure that tracks requests that are in conflict.
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The requests themselves are in the home tracker entries. The count is
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reported when an AAT entry deallocates.
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.It Li QHL_CONFLICT_CYCLES.IOH
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.Pq Event 25H , Umask 01H
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Counts cycles the Quickpath Home Logic IOH Tracker contains two or more
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requests with an address conflict. A max of 3 requests can be in conflict.
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.It Li QHL_CONFLICT_CYCLES.REMOTE
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.Pq Event 25H , Umask 02H
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Counts cycles the Quickpath Home Logic Remote Tracker contains two or more
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requests with an address conflict. A max of 3 requests can be in conflict.
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.It Li QHL_CONFLICT_CYCLES.LOCAL
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.Pq Event 25H , Umask 04H
|
|
Counts cycles the Quickpath Home Logic Local Tracker contains two or more
|
|
requests with an address conflict. A max of 3 requests can be in conflict.
|
|
.It Li QHL_TO_QMC_BYPASS
|
|
.Pq Event 26H , Umask 01H
|
|
Counts number or requests to the Quickpath Memory Controller that bypass the
|
|
Quickpath Home Logic. All local accesses can be bypassed. For remote
|
|
requests, only read requests can be bypassed.
|
|
.It Li QMC_NORMAL_FULL.READ.CH0
|
|
.Pq Event 27H , Umask 01H
|
|
Uncore cycles all the entries in the DRAM channel 0 medium or low priority
|
|
queue are occupied with read requests.
|
|
.It Li QMC_NORMAL_FULL.READ.CH1
|
|
.Pq Event 27H , Umask 02H
|
|
Uncore cycles all the entries in the DRAM channel 1 medium or low priority
|
|
queue are occupied with read requests.
|
|
.It Li QMC_NORMAL_FULL.READ.CH2
|
|
.Pq Event 27H , Umask 04H
|
|
Uncore cycles all the entries in the DRAM channel 2 medium or low priority
|
|
queue are occupied with read requests.
|
|
.It Li QMC_NORMAL_FULL.WRITE.CH0
|
|
.Pq Event 27H , Umask 08H
|
|
Uncore cycles all the entries in the DRAM channel 0 medium or low priority
|
|
queue are occupied with write requests.
|
|
.It Li QMC_NORMAL_FULL.WRITE.CH1
|
|
.Pq Event 27H , Umask 10H
|
|
Counts cycles all the entries in the DRAM channel 1 medium or low priority
|
|
queue are occupied with write requests.
|
|
.It Li QMC_NORMAL_FULL.WRITE.CH2
|
|
.Pq Event 27H , Umask 20H
|
|
Uncore cycles all the entries in the DRAM channel 2 medium or low priority
|
|
queue are occupied with write requests.
|
|
.It Li QMC_ISOC_FULL.READ.CH0
|
|
.Pq Event 28H , Umask 01H
|
|
Counts cycles all the entries in the DRAM channel 0 high priority queue are
|
|
occupied with isochronous read requests.
|
|
.It Li QMC_ISOC_FULL.READ.CH1
|
|
.Pq Event 28H , Umask 02H
|
|
Counts cycles all the entries in the DRAM channel 1 high priority queue are
|
|
occupied with isochronous read requests.
|
|
.It Li QMC_ISOC_FULL.READ.CH2
|
|
.Pq Event 28H , Umask 04H
|
|
Counts cycles all the entries in the DRAM channel 2 high priority queue are
|
|
occupied with isochronous read requests.
|
|
.It Li QMC_ISOC_FULL.WRITE.CH0
|
|
.Pq Event 28H , Umask 08H
|
|
Counts cycles all the entries in the DRAM channel 0 high priority queue are
|
|
occupied with isochronous write requests.
|
|
.It Li QMC_ISOC_FULL.WRITE.CH1
|
|
.Pq Event 28H , Umask 10H
|
|
Counts cycles all the entries in the DRAM channel 1 high priority queue are
|
|
occupied with isochronous write requests.
|
|
.It Li QMC_ISOC_FULL.WRITE.CH2
|
|
.Pq Event 28H , Umask 20H
|
|
Counts cycles all the entries in the DRAM channel 2 high priority queue are
|
|
occupied with isochronous write requests.
|
|
.It Li QMC_BUSY.READ.CH0
|
|
.Pq Event 29H , Umask 01H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
read request to DRAM channel 0.
|
|
.It Li QMC_BUSY.READ.CH1
|
|
.Pq Event 29H , Umask 02H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
read request to DRAM channel 1.
|
|
.It Li QMC_BUSY.READ.CH2
|
|
.Pq Event 29H , Umask 04H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
read request to DRAM channel 2.
|
|
.It Li QMC_BUSY.WRITE.CH0
|
|
.Pq Event 29H , Umask 08H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
write request to DRAM channel 0.
|
|
.It Li QMC_BUSY.WRITE.CH1
|
|
.Pq Event 29H , Umask 10H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
write request to DRAM channel 1.
|
|
.It Li QMC_BUSY.WRITE.CH2
|
|
.Pq Event 29H , Umask 20H
|
|
Counts cycles where Quickpath Memory Controller has at least 1 outstanding
|
|
write request to DRAM channel 2.
|
|
.It Li QMC_OCCUPANCY.CH0
|
|
.Pq Event 2AH , Umask 01H
|
|
IMC channel 0 normal read request occupancy.
|
|
.It Li QMC_OCCUPANCY.CH1
|
|
.Pq Event 2AH , Umask 02H
|
|
IMC channel 1 normal read request occupancy.
|
|
.It Li QMC_OCCUPANCY.CH2
|
|
.Pq Event 2AH , Umask 04H
|
|
IMC channel 2 normal read request occupancy.
|
|
.It Li QMC_ISSOC_OCCUPANCY.CH0
|
|
.Pq Event 2BH , Umask 01H
|
|
IMC channel 0 issoc read request occupancy.
|
|
.It Li QMC_ISSOC_OCCUPANCY.CH1
|
|
.Pq Event 2BH , Umask 02H
|
|
IMC channel 1 issoc read request occupancy.
|
|
.It Li QMC_ISSOC_OCCUPANCY.CH2
|
|
.Pq Event 2BH , Umask 04H
|
|
IMC channel 2 issoc read request occupancy.
|
|
.It Li QMC_ISSOC_READS.ANY
|
|
.Pq Event 2BH , Umask 07H
|
|
IMC issoc read request occupancy.
|
|
.It Li QMC_NORMAL_READS.CH0
|
|
.Pq Event 2CH , Umask 01H
|
|
Counts the number of Quickpath Memory Controller channel 0 medium and low
|
|
priority read requests. The QMC channel 0 normal read occupancy divided by
|
|
this count provides the average QMC channel 0 read latency.
|
|
.It Li QMC_NORMAL_READS.CH1
|
|
.Pq Event 2CH , Umask 02H
|
|
Counts the number of Quickpath Memory Controller channel 1 medium and low
|
|
priority read requests. The QMC channel 1 normal read occupancy divided by
|
|
this count provides the average QMC channel 1 read latency.
|
|
.It Li QMC_NORMAL_READS.CH2
|
|
.Pq Event 2CH , Umask 04H
|
|
Counts the number of Quickpath Memory Controller channel 2 medium and low
|
|
priority read requests. The QMC channel 2 normal read occupancy divided by
|
|
this count provides the average QMC channel 2 read latency.
|
|
.It Li QMC_NORMAL_READS.ANY
|
|
.Pq Event 2CH , Umask 07H
|
|
Counts the number of Quickpath Memory Controller medium and low priority
|
|
read requests. The QMC normal read occupancy divided by this count provides
|
|
the average QMC read latency.
|
|
.It Li QMC_HIGH_PRIORITY_READS.CH0
|
|
.Pq Event 2DH , Umask 01H
|
|
Counts the number of Quickpath Memory Controller channel 0 high priority
|
|
isochronous read requests.
|
|
.It Li QMC_HIGH_PRIORITY_READS.CH1
|
|
.Pq Event 2DH , Umask 02H
|
|
Counts the number of Quickpath Memory Controller channel 1 high priority
|
|
isochronous read requests.
|
|
.It Li QMC_HIGH_PRIORITY_READS.CH2
|
|
.Pq Event 2DH , Umask 04H
|
|
Counts the number of Quickpath Memory Controller channel 2 high priority
|
|
isochronous read requests.
|
|
.It Li QMC_HIGH_PRIORITY_READS.ANY
|
|
.Pq Event 2DH , Umask 07H
|
|
Counts the number of Quickpath Memory Controller high priority isochronous
|
|
read requests.
|
|
.It Li QMC_CRITICAL_PRIORITY_READS.CH0
|
|
.Pq Event 2EH , Umask 01H
|
|
Counts the number of Quickpath Memory Controller channel 0 critical priority
|
|
isochronous read requests.
|
|
.It Li QMC_CRITICAL_PRIORITY_READS.CH1
|
|
.Pq Event 2EH , Umask 02H
|
|
Counts the number of Quickpath Memory Controller channel 1 critical priority
|
|
isochronous read requests.
|
|
.It Li QMC_CRITICAL_PRIORITY_READS.CH2
|
|
.Pq Event 2EH , Umask 04H
|
|
Counts the number of Quickpath Memory Controller channel 2 critical priority
|
|
isochronous read requests.
|
|
.It Li QMC_CRITICAL_PRIORITY_READS.ANY
|
|
.Pq Event 2EH , Umask 07H
|
|
Counts the number of Quickpath Memory Controller critical priority
|
|
isochronous read requests.
|
|
.It Li QMC_WRITES.FULL.CH0
|
|
.Pq Event 2FH , Umask 01H
|
|
Counts number of full cache line writes to DRAM channel 0.
|
|
.It Li QMC_WRITES.FULL.CH1
|
|
.Pq Event 2FH , Umask 02H
|
|
Counts number of full cache line writes to DRAM channel 1.
|
|
.It Li QMC_WRITES.FULL.CH2
|
|
.Pq Event 2FH , Umask 04H
|
|
Counts number of full cache line writes to DRAM channel 2.
|
|
.It Li QMC_WRITES.FULL.ANY
|
|
.Pq Event 2FH , Umask 07H
|
|
Counts number of full cache line writes to DRAM.
|
|
.It Li QMC_WRITES.PARTIAL.CH0
|
|
.Pq Event 2FH , Umask 08H
|
|
Counts number of partial cache line writes to DRAM channel 0.
|
|
.It Li QMC_WRITES.PARTIAL.CH1
|
|
.Pq Event 2FH , Umask 10H
|
|
Counts number of partial cache line writes to DRAM channel 1.
|
|
.It Li QMC_WRITES.PARTIAL.CH2
|
|
.Pq Event 2FH , Umask 20H
|
|
Counts number of partial cache line writes to DRAM channel 2.
|
|
.It Li QMC_WRITES.PARTIAL.ANY
|
|
.Pq Event 2FH , Umask 38H
|
|
Counts number of partial cache line writes to DRAM.
|
|
.It Li QMC_CANCEL.CH0
|
|
.Pq Event 30H , Umask 01H
|
|
Counts number of DRAM channel 0 cancel requests.
|
|
.It Li QMC_CANCEL.CH1
|
|
.Pq Event 30H , Umask 02H
|
|
Counts number of DRAM channel 1 cancel requests.
|
|
.It Li QMC_CANCEL.CH2
|
|
.Pq Event 30H , Umask 04H
|
|
Counts number of DRAM channel 2 cancel requests.
|
|
.It Li QMC_CANCEL.ANY
|
|
.Pq Event 30H , Umask 07H
|
|
Counts number of DRAM cancel requests.
|
|
.It Li QMC_PRIORITY_UPDATES.CH0
|
|
.Pq Event 31H , Umask 01H
|
|
Counts number of DRAM channel 0 priority updates. A priority update occurs
|
|
when an ISOC high or critical request is received by the QHL and there is a
|
|
matching request with normal priority that has already been issued to the
|
|
QMC. In this instance, the QHL will send a priority update to QMC to
|
|
expedite the request.
|
|
.It Li QMC_PRIORITY_UPDATES.CH1
|
|
.Pq Event 31H , Umask 02H
|
|
Counts number of DRAM channel 1 priority updates. A priority update occurs
|
|
when an ISOC high or critical request is received by the QHL and there is a
|
|
matching request with normal priority that has already been issued to the
|
|
QMC. In this instance, the QHL will send a priority update to QMC to
|
|
expedite the request.
|
|
.It Li QMC_PRIORITY_UPDATES.CH2
|
|
.Pq Event 31H , Umask 04H
|
|
Counts number of DRAM channel 2 priority updates. A priority update occurs
|
|
when an ISOC high or critical request is received by the QHL and there is a
|
|
matching request with normal priority that has already been issued to the
|
|
QMC. In this instance, the QHL will send a priority update to QMC to
|
|
expedite the request.
|
|
.It Li QMC_PRIORITY_UPDATES.ANY
|
|
.Pq Event 31H , Umask 07H
|
|
Counts number of DRAM priority updates. A priority update occurs when an
|
|
ISOC high or critical request is received by the QHL and there is a matching
|
|
request with normal priority that has already been issued to the QMC. In
|
|
this instance, the QHL will send a priority update to QMC to expedite the
|
|
request.
|
|
.It Li QHL_FRC_ACK_CNFLTS.LOCAL
|
|
.Pq Event 33H , Umask 04H
|
|
Counts number of Force Acknowledge Conflict messages sent by the Quickpath
|
|
Home Logic to the local home.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0
|
|
.Pq Event 40H , Umask 01H
|
|
Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled
|
|
due to lack of a VNA and VN0 credit. Note that this event does not filter
|
|
out when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0
|
|
.Pq Event 40H , Umask 02H
|
|
Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled
|
|
due to lack of a VNA and VN0 credit. Note that this event does not filter
|
|
out when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0
|
|
.Pq Event 40H , Umask 04H
|
|
Counts cycles the Quickpath outbound link 0 non-data response virtual
|
|
channel is stalled due to lack of a VNA and VN0 credit. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1
|
|
.Pq Event 40H , Umask 08H
|
|
Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled
|
|
due to lack of a VNA and VN0 credit. Note that this event does not filter
|
|
out when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1
|
|
.Pq Event 40H , Umask 10H
|
|
Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled
|
|
due to lack of a VNA and VN0 credit. Note that this event does not filter
|
|
out when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1
|
|
.Pq Event 40H , Umask 20H
|
|
Counts cycles the Quickpath outbound link 1 non-data response virtual
|
|
channel is stalled due to lack of a VNA and VN0 credit. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0
|
|
.Pq Event 40H , Umask 07H
|
|
Counts cycles the Quickpath outbound link 0 virtual channels are stalled due
|
|
to lack of a VNA and VN0 credit. Note that this event does not filter out
|
|
when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1
|
|
.Pq Event 40H , Umask 38H
|
|
Counts cycles the Quickpath outbound link 1 virtual channels are stalled due
|
|
to lack of a VNA and VN0 credit. Note that this event does not filter out
|
|
when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0
|
|
.Pq Event 41H , Umask 01H
|
|
Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is
|
|
stalled due to lack of VNA and VN0 credits. Note that this event does not
|
|
filter out when a flit would not have been selected for arbitration because
|
|
another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0
|
|
.Pq Event 41H , Umask 02H
|
|
Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
|
|
channel is stalled due to lack of VNA and VN0 credits. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0
|
|
.Pq Event 41H , Umask 04H
|
|
Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
|
|
channel is stalled due to lack of VNA and VN0 credits. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1
|
|
.Pq Event 41H , Umask 08H
|
|
Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is
|
|
stalled due to lack of VNA and VN0 credits. Note that this event does not
|
|
filter out when a flit would not have been selected for arbitration because
|
|
another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1
|
|
.Pq Event 41H , Umask 10H
|
|
Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
|
|
channel is stalled due to lack of VNA and VN0 credits. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1
|
|
.Pq Event 41H , Umask 20H
|
|
Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
|
|
channel is stalled due to lack of VNA and VN0 credits. Note that this event
|
|
does not filter out when a flit would not have been selected for arbitration
|
|
because another virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0
|
|
.Pq Event 41H , Umask 07H
|
|
Counts cycles the Quickpath outbound link 0 virtual channels are stalled due
|
|
to lack of VNA and VN0 credits. Note that this event does not filter out
|
|
when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1
|
|
.Pq Event 41H , Umask 38H
|
|
Counts cycles the Quickpath outbound link 1 virtual channels are stalled due
|
|
to lack of VNA and VN0 credits. Note that this event does not filter out
|
|
when a flit would not have been selected for arbitration because another
|
|
virtual channel is getting arbitrated.
|
|
.It Li QPI_TX_HEADER.BUSY.LINK_0
|
|
.Pq Event 42H , Umask 02H
|
|
Number of cycles that the header buffer in the Quickpath Interface outbound
|
|
link 0 is busy.
|
|
.It Li QPI_TX_HEADER.BUSY.LINK_1
|
|
.Pq Event 42H , Umask 08H
|
|
Number of cycles that the header buffer in the Quickpath Interface outbound
|
|
link 1 is busy.
|
|
.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0
|
|
.Pq Event 43H , Umask 01H
|
|
Number of cycles that snoop packets incoming to the Quickpath Interface link
|
|
0 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
|
|
does not have any available entries.
|
|
.It Li QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1
|
|
.Pq Event 43H , Umask 02H
|
|
Number of cycles that snoop packets incoming to the Quickpath Interface link
|
|
1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
|
|
does not have any available entries.
|
|
.It Li DRAM_OPEN.CH0
|
|
.Pq Event 60H , Umask 01H
|
|
Counts number of DRAM Channel 0 open commands issued either for read or
|
|
write. To read or write data, the referenced DRAM page must first be opened.
|
|
.It Li DRAM_OPEN.CH1
|
|
.Pq Event 60H , Umask 02H
|
|
Counts number of DRAM Channel 1 open commands issued either for read or
|
|
write. To read or write data, the referenced DRAM page must first be opened.
|
|
.It Li DRAM_OPEN.CH2
|
|
.Pq Event 60H , Umask 04H
|
|
Counts number of DRAM Channel 2 open commands issued either for read or
|
|
write. To read or write data, the referenced DRAM page must first be opened.
|
|
.It Li DRAM_PAGE_CLOSE.CH0
|
|
.Pq Event 61H , Umask 01H
|
|
DRAM channel 0 command issued to CLOSE a page due to page idle timer
|
|
expiration. Closing a page is done by issuing a precharge.
|
|
.It Li DRAM_PAGE_CLOSE.CH1
|
|
.Pq Event 61H , Umask 02H
|
|
DRAM channel 1 command issued to CLOSE a page due to page idle timer
|
|
expiration. Closing a page is done by issuing a precharge.
|
|
.It Li DRAM_PAGE_CLOSE.CH2
|
|
.Pq Event 61H , Umask 04H
|
|
DRAM channel 2 command issued to CLOSE a page due to page idle timer
|
|
expiration. Closing a page is done by issuing a precharge.
|
|
.It Li DRAM_PAGE_MISS.CH0
|
|
.Pq Event 62H , Umask 01H
|
|
Counts the number of precharges (PRE) that were issued to DRAM channel 0
|
|
because there was a page miss. A page miss refers to a situation in which a
|
|
page is currently open and another page from the same bank needs to be
|
|
opened. The new page experiences a page miss. Closing of the old page is
|
|
done by issuing a precharge.
|
|
.It Li DRAM_PAGE_MISS.CH1
|
|
.Pq Event 62H , Umask 02H
|
|
Counts the number of precharges (PRE) that were issued to DRAM channel 1
|
|
because there was a page miss. A page miss refers to a situation in which a
|
|
page is currently open and another page from the same bank needs to be
|
|
opened. The new page experiences a page miss. Closing of the old page is
|
|
done by issuing a precharge.
|
|
.It Li DRAM_PAGE_MISS.CH2
|
|
.Pq Event 62H , Umask 04H
|
|
Counts the number of precharges (PRE) that were issued to DRAM channel 2
|
|
because there was a page miss. A page miss refers to a situation in which a
|
|
page is currently open and another page from the same bank needs to be
|
|
opened. The new page experiences a page miss. Closing of the old page is
|
|
done by issuing a precharge.
|
|
.It Li DRAM_READ_CAS.CH0
|
|
.Pq Event 63H , Umask 01H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 0.
|
|
.It Li DRAM_READ_CAS.AUTOPRE_CH0
|
|
.Pq Event 63H , Umask 02H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 0
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_READ_CAS.CH1
|
|
.Pq Event 63H , Umask 04H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 1.
|
|
.It Li DRAM_READ_CAS.AUTOPRE_CH1
|
|
.Pq Event 63H , Umask 08H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 1
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_READ_CAS.CH2
|
|
.Pq Event 63H , Umask 10H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 2.
|
|
.It Li DRAM_READ_CAS.AUTOPRE_CH2
|
|
.Pq Event 63H , Umask 20H
|
|
Counts the number of times a read CAS command was issued on DRAM channel 2
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_WRITE_CAS.CH0
|
|
.Pq Event 64H , Umask 01H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 0.
|
|
.It Li DRAM_WRITE_CAS.AUTOPRE_CH0
|
|
.Pq Event 64H , Umask 02H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 0
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_WRITE_CAS.CH1
|
|
.Pq Event 64H , Umask 04H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 1.
|
|
.It Li DRAM_WRITE_CAS.AUTOPRE_CH1
|
|
.Pq Event 64H , Umask 08H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 1
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_WRITE_CAS.CH2
|
|
.Pq Event 64H , Umask 10H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 2.
|
|
.It Li DRAM_WRITE_CAS.AUTOPRE_CH2
|
|
.Pq Event 64H , Umask 20H
|
|
Counts the number of times a write CAS command was issued on DRAM channel 2
|
|
where the command issued used the auto-precharge (auto page close) mode.
|
|
.It Li DRAM_REFRESH.CH0
|
|
.Pq Event 65H , Umask 01H
|
|
Counts number of DRAM channel 0 refresh commands. DRAM loses data content
|
|
over time. In order to keep correct data content, the data values have to be
|
|
refreshed periodically.
|
|
.It Li DRAM_REFRESH.CH1
|
|
.Pq Event 65H , Umask 02H
|
|
Counts number of DRAM channel 1 refresh commands. DRAM loses data content
|
|
over time. In order to keep correct data content, the data values have to be
|
|
refreshed periodically.
|
|
.It Li DRAM_REFRESH.CH2
|
|
.Pq Event 65H , Umask 04H
|
|
Counts number of DRAM channel 2 refresh commands. DRAM loses data content
|
|
over time. In order to keep correct data content, the data values have to be
|
|
refreshed periodically.
|
|
.It Li DRAM_PRE_ALL.CH0
|
|
.Pq Event 66H , Umask 01H
|
|
Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
|
|
all open pages in a rank. PREALL is issued when the DRAM needs to be
|
|
refreshed or needs to go into a power down mode.
|
|
.It Li DRAM_PRE_ALL.CH1
|
|
.Pq Event 66H , Umask 02H
|
|
Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
|
|
all open pages in a rank. PREALL is issued when the DRAM needs to be
|
|
refreshed or needs to go into a power down mode.
|
|
.It Li DRAM_PRE_ALL.CH2
|
|
.Pq Event 66H , Umask 04H
|
|
Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
|
|
all open pages in a rank. PREALL is issued when the DRAM needs to be
|
|
refreshed or needs to go into a power down mode.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr pmc 3 ,
|
|
.Xr pmc.atom 3 ,
|
|
.Xr pmc.core 3 ,
|
|
.Xr pmc.iaf 3 ,
|
|
.Xr pmc.ucf 3 ,
|
|
.Xr pmc.k7 3 ,
|
|
.Xr pmc.k8 3 ,
|
|
.Xr pmc.p4 3 ,
|
|
.Xr pmc.p5 3 ,
|
|
.Xr pmc.p6 3 ,
|
|
.Xr pmc.corei7 3 ,
|
|
.Xr pmc.westmere 3 ,
|
|
.Xr pmc.westmereuc 3 ,
|
|
.Xr pmc.soft 3 ,
|
|
.Xr pmc.tsc 3 ,
|
|
.Xr pmc_cpuinfo 3 ,
|
|
.Xr pmclog 3 ,
|
|
.Xr hwpmc 4
|
|
.Sh HISTORY
|
|
The
|
|
.Nm pmc
|
|
library first appeared in
|
|
.Fx 6.0 .
|
|
.Sh AUTHORS
|
|
The
|
|
.Lb libpmc
|
|
library was written by
|
|
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|