3e0732cf3e
The vlapic.ops handler 'enable_x2apic_mode' is called when the vlapic mode is switched to x2APIC. The VT-x implementation of this handler turns off the APIC-access virtualization and enables the x2APIC virtualization in the VMCS. The x2APIC virtualization is done by allowing guest read access to a subset of MSRs in the x2APIC range. In non-root operation the processor will satisfy an 'rdmsr' access to these MSRs by reading from the virtual APIC page instead. The guest is also given write access to TPR, EOI and SELF_IPI MSRs which get special treatment in non-root operation. This is documented in the Intel SDM section titled "Virtualizing MSR-Based APIC Accesses". Enforce that APIC-write and APIC-access VM-exits are handled only if APIC-access virtualization is enabled. The one exception to this is SELF_IPI virtualization which may result in an APIC-write VM-exit.
107 lines
4.3 KiB
C
107 lines
4.3 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VLAPIC_H_
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#define _VLAPIC_H_
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struct vm;
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enum x2apic_state;
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int vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
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uint64_t data, bool *retu);
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int vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
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uint64_t *data, bool *retu);
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/*
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* Returns 0 if there is no eligible vector that can be delivered to the
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* guest at this time and non-zero otherwise.
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*
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* If an eligible vector number is found and 'vecptr' is not NULL then it will
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* be stored in the location pointed to by 'vecptr'.
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*
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* Note that the vector does not automatically transition to the ISR as a
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* result of calling this function.
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*/
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int vlapic_pending_intr(struct vlapic *vlapic, int *vecptr);
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/*
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* Transition 'vector' from IRR to ISR. This function is called with the
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* vector returned by 'vlapic_pending_intr()' when the guest is able to
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* accept this interrupt (i.e. RFLAGS.IF = 1 and no conditions exist that
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* block interrupt delivery).
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*/
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void vlapic_intr_accepted(struct vlapic *vlapic, int vector);
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/*
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* Returns 1 if the vcpu needs to be notified of the interrupt and 0 otherwise.
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*/
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int vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level);
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/*
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* Post an interrupt to the vcpu running on 'hostcpu'. This will use a
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* hardware assist if available (e.g. Posted Interrupt) or fall back to
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* sending an 'ipinum' to interrupt the 'hostcpu'.
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*/
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void vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum);
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void vlapic_set_error(struct vlapic *vlapic, uint32_t mask);
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void vlapic_fire_cmci(struct vlapic *vlapic);
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int vlapic_trigger_lvt(struct vlapic *vlapic, int vector);
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uint64_t vlapic_get_apicbase(struct vlapic *vlapic);
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int vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val);
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void vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state s);
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bool vlapic_enabled(struct vlapic *vlapic);
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void vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
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int delmode, int vec);
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/* Reset the trigger-mode bits for all vectors to be edge-triggered */
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void vlapic_reset_tmr(struct vlapic *vlapic);
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/*
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* Set the trigger-mode bit associated with 'vector' to level-triggered if
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* the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
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* this 'vlapic'.
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*/
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void vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,
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int delmode, int vector);
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/* APIC write handlers */
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void vlapic_id_write_handler(struct vlapic *vlapic);
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void vlapic_ldr_write_handler(struct vlapic *vlapic);
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void vlapic_dfr_write_handler(struct vlapic *vlapic);
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void vlapic_svr_write_handler(struct vlapic *vlapic);
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void vlapic_esr_write_handler(struct vlapic *vlapic);
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int vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu);
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void vlapic_icrtmr_write_handler(struct vlapic *vlapic);
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void vlapic_dcr_write_handler(struct vlapic *vlapic);
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void vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset);
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void vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val);
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#endif /* _VLAPIC_H_ */
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