af9078c3f1
Submitted by: Andrew Lee <alee at solarflare.com> Sponsored by: Solarflare Communications, Inc. Approved by: gnn (mentor)
1126 lines
27 KiB
C
1126 lines
27 KiB
C
/*-
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* Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "efsys.h"
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#include "efx.h"
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#include "efx_types.h"
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#include "efx_regs.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_QSTATS
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#define EFX_EV_QSTAT_INCR(_eep, _stat) \
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do { \
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(_eep)->ee_stat[_stat]++; \
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_NOTE(CONSTANTCONDITION) \
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} while (B_FALSE)
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#else
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#define EFX_EV_QSTAT_INCR(_eep, _stat)
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#endif
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__checkReturn int
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efx_ev_init(
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__in efx_nic_t *enp)
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{
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efx_oword_t oword;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
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if (enp->en_mod_flags & EFX_MOD_EV) {
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rc = EINVAL;
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goto fail1;
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}
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EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
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/*
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* Program the event queue for receive and transmit queue
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* flush events.
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*/
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EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
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enp->en_mod_flags |= EFX_MOD_EV;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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static __checkReturn boolean_t
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efx_ev_rx_not_ok(
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__in efx_evq_t *eep,
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__in efx_qword_t *eqp,
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__in uint32_t label,
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__in uint32_t id,
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__inout uint16_t *flagsp)
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{
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boolean_t ignore = B_FALSE;
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
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EFSYS_PROBE(tobe_disc);
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/*
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* Assume this is a unicast address mismatch, unless below
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* we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
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* EV_RX_PAUSE_FRM_ERR is set.
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*/
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(*flagsp) |= EFX_ADDR_MISMATCH;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
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EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
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EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
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(*flagsp) |= EFX_DISCARD;
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#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
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/*
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* Lookout for payload queue ran dry errors and ignore them.
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*
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* Sadly for the header/data split cases, the descriptor
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* pointer in this event refers to the header queue and
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* therefore cannot be easily detected as duplicate.
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* So we drop these and rely on the receive processing seeing
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* a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
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* the partially received packet.
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*/
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if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
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(EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
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(EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
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ignore = B_TRUE;
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#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
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EFSYS_PROBE(crc_err);
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(*flagsp) &= ~EFX_ADDR_MISMATCH;
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(*flagsp) |= EFX_DISCARD;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
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EFSYS_PROBE(pause_frm_err);
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(*flagsp) &= ~EFX_ADDR_MISMATCH;
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(*flagsp) |= EFX_DISCARD;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
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EFSYS_PROBE(owner_id_err);
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(*flagsp) |= EFX_DISCARD;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
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EFSYS_PROBE(ipv4_err);
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(*flagsp) &= ~EFX_CKSUM_IPV4;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
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EFSYS_PROBE(udp_chk_err);
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(*flagsp) &= ~EFX_CKSUM_TCPUDP;
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
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/*
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* If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
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* causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
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* condition.
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*/
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(*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
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}
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return (ignore);
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}
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static __checkReturn boolean_t
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efx_ev_rx(
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__in efx_evq_t *eep,
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__in efx_qword_t *eqp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg)
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{
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efx_nic_t *enp = eep->ee_enp;
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uint32_t id;
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uint32_t size;
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uint32_t label;
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boolean_t ok;
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#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
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boolean_t sop;
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boolean_t jumbo_cont;
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#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
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uint32_t hdr_type;
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boolean_t is_v6;
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uint16_t flags;
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boolean_t ignore;
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boolean_t should_abort;
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EFX_EV_QSTAT_INCR(eep, EV_RX);
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/* Basic packet information */
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id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
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size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
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label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
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ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
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#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
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sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
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jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
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#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
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hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
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is_v6 = (enp->en_family != EFX_FAMILY_FALCON &&
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EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
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/*
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* If packet is marked as OK and packet type is TCP/IP or
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* UDP/IP or other IP, then we can rely on the hardware checksums.
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*/
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switch (hdr_type) {
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case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
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flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
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if (is_v6) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
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flags |= EFX_PKT_IPV6;
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} else {
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EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
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flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
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}
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break;
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case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
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flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
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if (is_v6) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
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flags |= EFX_PKT_IPV6;
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} else {
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EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
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flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
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}
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break;
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case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
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if (is_v6) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
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flags = EFX_PKT_IPV6;
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} else {
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EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
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flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
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}
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break;
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case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
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EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
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flags = 0;
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break;
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default:
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EFSYS_ASSERT(B_FALSE);
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flags = 0;
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break;
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}
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#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT
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/* Report scatter and header/lookahead split buffer flags */
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if (sop)
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flags |= EFX_PKT_START;
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if (jumbo_cont)
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flags |= EFX_PKT_CONT;
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#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */
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/* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
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if (!ok) {
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ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags);
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if (ignore) {
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EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
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uint32_t, size, uint16_t, flags);
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return (B_FALSE);
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}
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}
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/* If we're not discarding the packet then it is ok */
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if (~flags & EFX_DISCARD)
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EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
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/* Detect multicast packets that didn't match the filter */
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
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} else {
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EFSYS_PROBE(mcast_mismatch);
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flags |= EFX_ADDR_MISMATCH;
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}
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} else {
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flags |= EFX_PKT_UNICAST;
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}
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/*
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* The packet parser in Siena can abort parsing packets under
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* certain error conditions, setting the PKT_NOT_PARSED bit
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* (which clears PKT_OK). If this is set, then don't trust
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* the PKT_TYPE field.
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*/
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if (enp->en_family != EFX_FAMILY_FALCON && !ok) {
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uint32_t parse_err;
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parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
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if (parse_err != 0)
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flags |= EFX_CHECK_VLAN;
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}
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if (~flags & EFX_CHECK_VLAN) {
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uint32_t pkt_type;
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pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
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if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
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flags |= EFX_PKT_VLAN_TAGGED;
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}
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EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
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uint32_t, size, uint16_t, flags);
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EFSYS_ASSERT(eecp->eec_rx != NULL);
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should_abort = eecp->eec_rx(arg, label, id, size, flags);
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return (should_abort);
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}
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static __checkReturn boolean_t
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efx_ev_tx(
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__in efx_evq_t *eep,
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__in efx_qword_t *eqp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg)
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{
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uint32_t id;
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uint32_t label;
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boolean_t should_abort;
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EFX_EV_QSTAT_INCR(eep, EV_TX);
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
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EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
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EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
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EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
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id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
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label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
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EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
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EFSYS_ASSERT(eecp->eec_tx != NULL);
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should_abort = eecp->eec_tx(arg, label, id);
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return (should_abort);
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}
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
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EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
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uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
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uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
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EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
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EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
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if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
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EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
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EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
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return (B_FALSE);
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}
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static __checkReturn boolean_t
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efx_ev_global(
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__in efx_evq_t *eep,
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__in efx_qword_t *eqp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg)
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{
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efx_nic_t *enp = eep->ee_enp;
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efx_port_t *epp = &(enp->en_port);
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boolean_t should_abort;
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EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
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should_abort = B_FALSE;
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/* Check for a link management event */
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if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) {
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EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT);
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EFSYS_PROBE(xg_mgt);
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epp->ep_mac_poll_needed = B_TRUE;
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}
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return (should_abort);
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}
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|
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static __checkReturn boolean_t
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efx_ev_driver(
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__in efx_evq_t *eep,
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__in efx_qword_t *eqp,
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__in const efx_ev_callbacks_t *eecp,
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__in_opt void *arg)
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{
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boolean_t should_abort;
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EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
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should_abort = B_FALSE;
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switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
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case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
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uint32_t txq_index;
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EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
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txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
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EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
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EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
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should_abort = eecp->eec_txq_flush_done(arg, txq_index);
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break;
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}
|
|
case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
|
|
uint32_t rxq_index;
|
|
uint32_t failed;
|
|
|
|
rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
|
|
failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
|
|
|
|
EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
|
|
EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
|
|
|
|
if (failed) {
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
|
|
|
|
EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
|
|
|
|
should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index);
|
|
} else {
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
|
|
|
|
EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
|
|
|
|
should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
|
|
}
|
|
|
|
break;
|
|
}
|
|
case FSE_AZ_EVQ_INIT_DONE_EV:
|
|
EFSYS_ASSERT(eecp->eec_initialized != NULL);
|
|
should_abort = eecp->eec_initialized(arg);
|
|
|
|
break;
|
|
|
|
case FSE_AZ_EVQ_NOT_EN_EV:
|
|
EFSYS_PROBE(evq_not_en);
|
|
break;
|
|
|
|
case FSE_AZ_SRM_UPD_DONE_EV: {
|
|
uint32_t code;
|
|
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
|
|
|
|
code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
|
|
|
|
EFSYS_ASSERT(eecp->eec_sram != NULL);
|
|
should_abort = eecp->eec_sram(arg, code);
|
|
|
|
break;
|
|
}
|
|
case FSE_AZ_WAKE_UP_EV: {
|
|
uint32_t id;
|
|
|
|
id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
|
|
|
|
EFSYS_ASSERT(eecp->eec_wake_up != NULL);
|
|
should_abort = eecp->eec_wake_up(arg, id);
|
|
|
|
break;
|
|
}
|
|
case FSE_AZ_TX_PKT_NON_TCP_UDP:
|
|
EFSYS_PROBE(tx_pkt_non_tcp_udp);
|
|
break;
|
|
|
|
case FSE_AZ_TIMER_EV: {
|
|
uint32_t id;
|
|
|
|
id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
|
|
|
|
EFSYS_ASSERT(eecp->eec_timer != NULL);
|
|
should_abort = eecp->eec_timer(arg, id);
|
|
|
|
break;
|
|
}
|
|
case FSE_AZ_RX_DSC_ERROR_EV:
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
|
|
|
|
EFSYS_PROBE(rx_dsc_error);
|
|
|
|
EFSYS_ASSERT(eecp->eec_exception != NULL);
|
|
should_abort = eecp->eec_exception(arg,
|
|
EFX_EXCEPTION_RX_DSC_ERROR, 0);
|
|
|
|
break;
|
|
|
|
case FSE_AZ_TX_DSC_ERROR_EV:
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
|
|
|
|
EFSYS_PROBE(tx_dsc_error);
|
|
|
|
EFSYS_ASSERT(eecp->eec_exception != NULL);
|
|
should_abort = eecp->eec_exception(arg,
|
|
EFX_EXCEPTION_TX_DSC_ERROR, 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return (should_abort);
|
|
}
|
|
|
|
static __checkReturn boolean_t
|
|
efx_ev_drv_gen(
|
|
__in efx_evq_t *eep,
|
|
__in efx_qword_t *eqp,
|
|
__in const efx_ev_callbacks_t *eecp,
|
|
__in_opt void *arg)
|
|
{
|
|
uint32_t data;
|
|
boolean_t should_abort;
|
|
|
|
EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
|
|
|
|
data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
|
|
if (data >= ((uint32_t)1 << 16)) {
|
|
EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
|
|
uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
|
|
uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
|
|
return (B_TRUE);
|
|
}
|
|
|
|
EFSYS_ASSERT(eecp->eec_software != NULL);
|
|
should_abort = eecp->eec_software(arg, (uint16_t)data);
|
|
|
|
return (should_abort);
|
|
}
|
|
|
|
#if EFSYS_OPT_MCDI
|
|
|
|
static __checkReturn boolean_t
|
|
efx_ev_mcdi(
|
|
__in efx_evq_t *eep,
|
|
__in efx_qword_t *eqp,
|
|
__in const efx_ev_callbacks_t *eecp,
|
|
__in_opt void *arg)
|
|
{
|
|
efx_nic_t *enp = eep->ee_enp;
|
|
unsigned code;
|
|
boolean_t should_abort = B_FALSE;
|
|
|
|
EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
|
|
|
|
if (enp->en_family != EFX_FAMILY_SIENA)
|
|
goto out;
|
|
|
|
EFSYS_ASSERT(eecp->eec_link_change != NULL);
|
|
EFSYS_ASSERT(eecp->eec_exception != NULL);
|
|
#if EFSYS_OPT_MON_STATS
|
|
EFSYS_ASSERT(eecp->eec_monitor != NULL);
|
|
#endif
|
|
|
|
EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
|
|
|
|
code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
|
|
switch (code) {
|
|
case MCDI_EVENT_CODE_BADSSERT:
|
|
efx_mcdi_ev_death(enp, EINTR);
|
|
break;
|
|
|
|
case MCDI_EVENT_CODE_CMDDONE:
|
|
efx_mcdi_ev_cpl(enp,
|
|
MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
|
|
MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
|
|
MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
|
|
break;
|
|
|
|
case MCDI_EVENT_CODE_LINKCHANGE: {
|
|
efx_link_mode_t link_mode;
|
|
|
|
siena_phy_link_ev(enp, eqp, &link_mode);
|
|
should_abort = eecp->eec_link_change(arg, link_mode);
|
|
break;
|
|
}
|
|
case MCDI_EVENT_CODE_SENSOREVT: {
|
|
#if EFSYS_OPT_MON_STATS
|
|
efx_mon_stat_t id;
|
|
efx_mon_stat_value_t value;
|
|
int rc;
|
|
|
|
if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0)
|
|
should_abort = eecp->eec_monitor(arg, id, value);
|
|
else if (rc == ENOTSUP) {
|
|
should_abort = eecp->eec_exception(arg,
|
|
EFX_EXCEPTION_UNKNOWN_SENSOREVT,
|
|
MCDI_EV_FIELD(eqp, DATA));
|
|
} else
|
|
EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
|
|
#else
|
|
should_abort = B_FALSE;
|
|
#endif
|
|
break;
|
|
}
|
|
case MCDI_EVENT_CODE_SCHEDERR:
|
|
/* Informational only */
|
|
break;
|
|
|
|
case MCDI_EVENT_CODE_REBOOT:
|
|
efx_mcdi_ev_death(enp, EIO);
|
|
break;
|
|
|
|
case MCDI_EVENT_CODE_MAC_STATS_DMA:
|
|
#if EFSYS_OPT_MAC_STATS
|
|
if (eecp->eec_mac_stats != NULL) {
|
|
eecp->eec_mac_stats(arg,
|
|
MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
|
|
}
|
|
#endif
|
|
break;
|
|
|
|
case MCDI_EVENT_CODE_FWALERT: {
|
|
uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
|
|
|
|
if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
|
|
should_abort = eecp->eec_exception(arg,
|
|
EFX_EXCEPTION_FWALERT_SRAM,
|
|
MCDI_EV_FIELD(eqp, FWALERT_DATA));
|
|
else
|
|
should_abort = eecp->eec_exception(arg,
|
|
EFX_EXCEPTION_UNKNOWN_FWALERT,
|
|
MCDI_EV_FIELD(eqp, DATA));
|
|
break;
|
|
}
|
|
|
|
default:
|
|
EFSYS_PROBE1(mc_pcol_error, int, code);
|
|
break;
|
|
}
|
|
|
|
out:
|
|
return (should_abort);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_MCDI */
|
|
|
|
__checkReturn int
|
|
efx_ev_qprime(
|
|
__in efx_evq_t *eep,
|
|
__in unsigned int count)
|
|
{
|
|
efx_nic_t *enp = eep->ee_enp;
|
|
uint32_t rptr;
|
|
efx_dword_t dword;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
rptr = count & eep->ee_mask;
|
|
|
|
EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
|
|
|
|
EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
|
|
&dword, B_FALSE);
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn boolean_t
|
|
efx_ev_qpending(
|
|
__in efx_evq_t *eep,
|
|
__in unsigned int count)
|
|
{
|
|
size_t offset;
|
|
efx_qword_t qword;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
|
|
EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
|
|
|
|
return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff &&
|
|
EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff);
|
|
}
|
|
|
|
#if EFSYS_OPT_EV_PREFETCH
|
|
|
|
void
|
|
efx_ev_qprefetch(
|
|
__in efx_evq_t *eep,
|
|
__in unsigned int count)
|
|
{
|
|
unsigned int offset;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
|
|
EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_EV_PREFETCH */
|
|
|
|
#define EFX_EV_BATCH 8
|
|
|
|
#define EFX_EV_PRESENT(_qword) \
|
|
(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
|
|
EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
|
|
|
|
void
|
|
efx_ev_qpoll(
|
|
__in efx_evq_t *eep,
|
|
__inout unsigned int *countp,
|
|
__in const efx_ev_callbacks_t *eecp,
|
|
__in_opt void *arg)
|
|
{
|
|
efx_qword_t ev[EFX_EV_BATCH];
|
|
unsigned int batch;
|
|
unsigned int total;
|
|
unsigned int count;
|
|
unsigned int index;
|
|
size_t offset;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
EFSYS_ASSERT(countp != NULL);
|
|
EFSYS_ASSERT(eecp != NULL);
|
|
|
|
count = *countp;
|
|
do {
|
|
/* Read up until the end of the batch period */
|
|
batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
|
|
offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
|
|
for (total = 0; total < batch; ++total) {
|
|
EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
|
|
|
|
if (!EFX_EV_PRESENT(ev[total]))
|
|
break;
|
|
|
|
EFSYS_PROBE3(event, unsigned int, eep->ee_index,
|
|
uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
|
|
uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
|
|
|
|
offset += sizeof (efx_qword_t);
|
|
}
|
|
|
|
#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
|
|
/*
|
|
* Prefetch the next batch when we get within PREFETCH_PERIOD
|
|
* of a completed batch. If the batch is smaller, then prefetch
|
|
* immediately.
|
|
*/
|
|
if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
|
|
EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
|
|
#endif /* EFSYS_OPT_EV_PREFETCH */
|
|
|
|
/* Process the batch of events */
|
|
for (index = 0; index < total; ++index) {
|
|
boolean_t should_abort;
|
|
uint32_t code;
|
|
efx_ev_handler_t handler;
|
|
|
|
#if EFSYS_OPT_EV_PREFETCH
|
|
/* Prefetch if we've now reached the batch period */
|
|
if (total == batch &&
|
|
index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
|
|
offset = (count + batch) & eep->ee_mask;
|
|
offset *= sizeof (efx_qword_t);
|
|
|
|
EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
|
|
}
|
|
#endif /* EFSYS_OPT_EV_PREFETCH */
|
|
|
|
EFX_EV_QSTAT_INCR(eep, EV_ALL);
|
|
|
|
code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
|
|
handler = eep->ee_handler[code];
|
|
EFSYS_ASSERT(handler != NULL);
|
|
should_abort = handler(eep, &(ev[index]), eecp, arg);
|
|
if (should_abort) {
|
|
/* Ignore subsequent events */
|
|
total = index + 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Now that the hardware has most likely moved onto dma'ing
|
|
* into the next cache line, clear the processed events. Take
|
|
* care to only clear out events that we've processed
|
|
*/
|
|
EFX_SET_QWORD(ev[0]);
|
|
offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
|
|
for (index = 0; index < total; ++index) {
|
|
EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
|
|
offset += sizeof (efx_qword_t);
|
|
}
|
|
|
|
count += total;
|
|
|
|
} while (total == batch);
|
|
|
|
*countp = count;
|
|
}
|
|
|
|
void
|
|
efx_ev_qpost(
|
|
__in efx_evq_t *eep,
|
|
__in uint16_t data)
|
|
{
|
|
efx_nic_t *enp = eep->ee_enp;
|
|
efx_qword_t ev;
|
|
efx_oword_t oword;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
|
|
FSF_AZ_EV_DATA_DW0, (uint32_t)data);
|
|
|
|
EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
|
|
EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
|
|
EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
|
|
|
|
EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_ev_qmoderate(
|
|
__in efx_evq_t *eep,
|
|
__in unsigned int us)
|
|
{
|
|
efx_nic_t *enp = eep->ee_enp;
|
|
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
|
|
unsigned int locked;
|
|
efx_dword_t dword;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
if (us > encp->enc_evq_timer_max_us) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
/* If the value is zero then disable the timer */
|
|
if (us == 0) {
|
|
if (enp->en_family == EFX_FAMILY_FALCON)
|
|
EFX_POPULATE_DWORD_2(dword,
|
|
FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS,
|
|
FRF_AB_TC_TIMER_VAL, 0);
|
|
else
|
|
EFX_POPULATE_DWORD_2(dword,
|
|
FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
|
|
FRF_CZ_TC_TIMER_VAL, 0);
|
|
} else {
|
|
uint32_t timer_val;
|
|
|
|
/* Calculate the timer value in quanta */
|
|
timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
|
|
|
|
/* Moderation value is base 0 so we need to deduct 1 */
|
|
if (timer_val > 0)
|
|
timer_val--;
|
|
|
|
if (enp->en_family == EFX_FAMILY_FALCON)
|
|
EFX_POPULATE_DWORD_2(dword,
|
|
FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF,
|
|
FRF_AB_TIMER_VAL, timer_val);
|
|
else
|
|
EFX_POPULATE_DWORD_2(dword,
|
|
FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
|
|
FRF_CZ_TC_TIMER_VAL, timer_val);
|
|
}
|
|
|
|
locked = (eep->ee_index == 0) ? 1 : 0;
|
|
|
|
EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
|
|
eep->ee_index, &dword, locked);
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_ev_qcreate(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int index,
|
|
__in efsys_mem_t *esmp,
|
|
__in size_t n,
|
|
__in uint32_t id,
|
|
__deref_out efx_evq_t **eepp)
|
|
{
|
|
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
|
|
uint32_t size;
|
|
efx_evq_t *eep;
|
|
efx_oword_t oword;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
|
|
|
|
EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
|
|
|
|
if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
if (index >= encp->enc_evq_limit) {
|
|
rc = EINVAL;
|
|
goto fail2;
|
|
}
|
|
#if EFSYS_OPT_RX_SCALE
|
|
if (enp->en_intr.ei_type == EFX_INTR_LINE &&
|
|
index >= EFX_MAXRSS_LEGACY) {
|
|
rc = EINVAL;
|
|
goto fail3;
|
|
}
|
|
#endif
|
|
for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
|
|
size++)
|
|
if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
|
|
break;
|
|
if (id + (1 << size) >= encp->enc_buftbl_limit) {
|
|
rc = EINVAL;
|
|
goto fail4;
|
|
}
|
|
|
|
/* Allocate an EVQ object */
|
|
EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
|
|
if (eep == NULL) {
|
|
rc = ENOMEM;
|
|
goto fail5;
|
|
}
|
|
|
|
eep->ee_magic = EFX_EVQ_MAGIC;
|
|
eep->ee_enp = enp;
|
|
eep->ee_index = index;
|
|
eep->ee_mask = n - 1;
|
|
eep->ee_esmp = esmp;
|
|
|
|
/* Set up the handler table */
|
|
eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx;
|
|
eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx;
|
|
eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver;
|
|
eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global;
|
|
eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen;
|
|
#if EFSYS_OPT_MCDI
|
|
eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi;
|
|
#endif /* EFSYS_OPT_MCDI */
|
|
|
|
/* Set up the new event queue */
|
|
if (enp->en_family != EFX_FAMILY_FALCON) {
|
|
EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
|
|
EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword);
|
|
}
|
|
|
|
EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
|
|
FRF_AZ_EVQ_BUF_BASE_ID, id);
|
|
|
|
EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword);
|
|
|
|
enp->en_ev_qcount++;
|
|
*eepp = eep;
|
|
return (0);
|
|
|
|
fail5:
|
|
EFSYS_PROBE(fail5);
|
|
fail4:
|
|
EFSYS_PROBE(fail4);
|
|
#if EFSYS_OPT_RX_SCALE
|
|
fail3:
|
|
EFSYS_PROBE(fail3);
|
|
#endif
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
#if EFSYS_OPT_QSTATS
|
|
#if EFSYS_OPT_NAMES
|
|
/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */
|
|
static const char __cs * __cs __efx_ev_qstat_name[] = {
|
|
"all",
|
|
"rx",
|
|
"rx_ok",
|
|
"rx_recovery",
|
|
"rx_frm_trunc",
|
|
"rx_tobe_disc",
|
|
"rx_pause_frm_err",
|
|
"rx_buf_owner_id_err",
|
|
"rx_ipv4_hdr_chksum_err",
|
|
"rx_tcp_udp_chksum_err",
|
|
"rx_eth_crc_err",
|
|
"rx_ip_frag_err",
|
|
"rx_mcast_pkt",
|
|
"rx_mcast_hash_match",
|
|
"rx_tcp_ipv4",
|
|
"rx_tcp_ipv6",
|
|
"rx_udp_ipv4",
|
|
"rx_udp_ipv6",
|
|
"rx_other_ipv4",
|
|
"rx_other_ipv6",
|
|
"rx_non_ip",
|
|
"rx_overrun",
|
|
"tx",
|
|
"tx_wq_ff_full",
|
|
"tx_pkt_err",
|
|
"tx_pkt_too_big",
|
|
"tx_unexpected",
|
|
"global",
|
|
"global_phy",
|
|
"global_mnt",
|
|
"global_rx_recovery",
|
|
"driver",
|
|
"driver_srm_upd_done",
|
|
"driver_tx_descq_fls_done",
|
|
"driver_rx_descq_fls_done",
|
|
"driver_rx_descq_fls_failed",
|
|
"driver_rx_dsc_error",
|
|
"driver_tx_dsc_error",
|
|
"drv_gen",
|
|
"mcdi_response",
|
|
};
|
|
/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
|
|
|
|
const char __cs *
|
|
efx_ev_qstat_name(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int id)
|
|
{
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(id, <, EV_NQSTATS);
|
|
|
|
return (__efx_ev_qstat_name[id]);
|
|
}
|
|
#endif /* EFSYS_OPT_NAMES */
|
|
#endif /* EFSYS_OPT_QSTATS */
|
|
|
|
#if EFSYS_OPT_QSTATS
|
|
void
|
|
efx_ev_qstats_update(
|
|
__in efx_evq_t *eep,
|
|
__inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
|
|
{
|
|
unsigned int id;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
for (id = 0; id < EV_NQSTATS; id++) {
|
|
efsys_stat_t *essp = &stat[id];
|
|
|
|
EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
|
|
eep->ee_stat[id] = 0;
|
|
}
|
|
}
|
|
#endif /* EFSYS_OPT_QSTATS */
|
|
|
|
void
|
|
efx_ev_qdestroy(
|
|
__in efx_evq_t *eep)
|
|
{
|
|
efx_nic_t *enp = eep->ee_enp;
|
|
efx_oword_t oword;
|
|
|
|
EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
|
|
|
|
EFSYS_ASSERT(enp->en_ev_qcount != 0);
|
|
--enp->en_ev_qcount;
|
|
|
|
/* Purge event queue */
|
|
EFX_ZERO_OWORD(oword);
|
|
|
|
EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
|
|
eep->ee_index, &oword);
|
|
|
|
if (enp->en_family != EFX_FAMILY_FALCON) {
|
|
EFX_ZERO_OWORD(oword);
|
|
EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
|
|
eep->ee_index, &oword);
|
|
}
|
|
|
|
/* Free the EVQ object */
|
|
EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
|
|
}
|
|
|
|
void
|
|
efx_ev_fini(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
|
|
EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
|
|
EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
|
|
EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
|
|
|
|
enp->en_mod_flags &= ~EFX_MOD_EV;
|
|
}
|