c071447ac1
Sync endif comment with conditional. BOOTROM and SIENA_BOOTROM are the same, but highlight that it is Siena. Restore commented out assertion. Sync comments with out-of-tree driver. Sponsored by: Solarflare Communications, Inc. Approved by: gnn (mentor)
682 lines
15 KiB
C
682 lines
15 KiB
C
/*-
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* Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "efsys.h"
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#include "efx.h"
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#include "efx_types.h"
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#include "efx_regs.h"
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#include "efx_impl.h"
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__checkReturn int
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efx_family(
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__in uint16_t venid,
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__in uint16_t devid,
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__out efx_family_t *efp)
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{
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#if EFSYS_OPT_FALCON
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if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_FALCON) {
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*efp = EFX_FAMILY_FALCON;
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return (0);
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}
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#endif
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#if EFSYS_OPT_SIENA
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if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_BETHPAGE) {
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*efp = EFX_FAMILY_SIENA;
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return (0);
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}
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if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_SIENA) {
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*efp = EFX_FAMILY_SIENA;
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return (0);
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}
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if (venid == EFX_PCI_VENID_SFC &&
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devid == EFX_PCI_DEVID_SIENA_F1_UNINIT) {
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*efp = EFX_FAMILY_SIENA;
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return (0);
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}
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#endif
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return (ENOTSUP);
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}
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/*
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* To support clients which aren't provided with any PCI context infer
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* the hardware family by inspecting the hardware. Obviously the caller
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* must be damn sure they're really talking to a supported device.
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*/
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__checkReturn int
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efx_infer_family(
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__in efsys_bar_t *esbp,
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__out efx_family_t *efp)
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{
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efx_family_t family;
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efx_oword_t oword;
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unsigned int portnum;
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int rc;
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EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE);
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portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
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switch (portnum) {
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#if EFSYS_OPT_FALCON
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case 0:
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family = EFX_FAMILY_FALCON;
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break;
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#endif
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#if EFSYS_OPT_SIENA
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case 1:
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case 2:
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family = EFX_FAMILY_SIENA;
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break;
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#endif
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default:
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rc = ENOTSUP;
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goto fail1;
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}
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if (efp != NULL)
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*efp = family;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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/*
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* The built-in default value device id for port 1 of Siena is 0x0810.
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* manftest needs to be able to cope with that.
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*/
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#define EFX_BIU_MAGIC0 0x01234567
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#define EFX_BIU_MAGIC1 0xfedcba98
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static __checkReturn int
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efx_nic_biu_test(
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__in efx_nic_t *enp)
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{
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efx_oword_t oword;
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int rc;
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/*
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* Write magic values to scratch registers 0 and 1, then
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* verify that the values were written correctly. Interleave
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* the accesses to ensure that the BIU is not just reading
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* back the cached value that was last written.
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*/
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
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EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
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if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
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rc = EIO;
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goto fail1;
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}
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EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
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if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
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rc = EIO;
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goto fail2;
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}
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/*
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* Perform the same test, with the values swapped. This
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* ensures that subsequent tests don't start with the correct
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* values already written into the scratch registers.
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*/
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
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EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
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if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
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rc = EIO;
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goto fail3;
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}
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EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
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if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
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rc = EIO;
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goto fail4;
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}
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return (0);
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fail4:
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EFSYS_PROBE(fail4);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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#if EFSYS_OPT_FALCON
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static efx_nic_ops_t __cs __efx_nic_falcon_ops = {
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falcon_nic_probe, /* eno_probe */
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falcon_nic_reset, /* eno_reset */
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falcon_nic_init, /* eno_init */
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#if EFSYS_OPT_DIAG
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falcon_sram_test, /* eno_sram_test */
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falcon_nic_register_test, /* eno_register_test */
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#endif /* EFSYS_OPT_DIAG */
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falcon_nic_fini, /* eno_fini */
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falcon_nic_unprobe, /* eno_unprobe */
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};
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#endif /* EFSYS_OPT_FALCON */
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#if EFSYS_OPT_SIENA
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static efx_nic_ops_t __cs __efx_nic_siena_ops = {
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siena_nic_probe, /* eno_probe */
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siena_nic_reset, /* eno_reset */
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siena_nic_init, /* eno_init */
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#if EFSYS_OPT_DIAG
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siena_sram_test, /* eno_sram_test */
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siena_nic_register_test, /* eno_register_test */
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#endif /* EFSYS_OPT_DIAG */
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siena_nic_fini, /* eno_fini */
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siena_nic_unprobe, /* eno_unprobe */
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};
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#endif /* EFSYS_OPT_SIENA */
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__checkReturn int
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efx_nic_create(
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__in efx_family_t family,
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__in efsys_identifier_t *esip,
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__in efsys_bar_t *esbp,
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__in efsys_lock_t *eslp,
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__deref_out efx_nic_t **enpp)
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{
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efx_nic_t *enp;
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int rc;
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EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
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EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
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/* Allocate a NIC object */
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EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
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if (enp == NULL) {
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rc = ENOMEM;
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goto fail1;
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}
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enp->en_magic = EFX_NIC_MAGIC;
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switch (family) {
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#if EFSYS_OPT_FALCON
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case EFX_FAMILY_FALCON:
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enp->en_enop = (efx_nic_ops_t *)&__efx_nic_falcon_ops;
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enp->en_features = 0;
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break;
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#endif /* EFSYS_OPT_FALCON */
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#if EFSYS_OPT_SIENA
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case EFX_FAMILY_SIENA:
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enp->en_enop = (efx_nic_ops_t *)&__efx_nic_siena_ops;
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enp->en_features =
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EFX_FEATURE_IPV6 |
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EFX_FEATURE_LFSR_HASH_INSERT |
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EFX_FEATURE_LINK_EVENTS |
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EFX_FEATURE_PERIODIC_MAC_STATS |
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EFX_FEATURE_WOL |
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EFX_FEATURE_MCDI |
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EFX_FEATURE_LOOKAHEAD_SPLIT |
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EFX_FEATURE_MAC_HEADER_FILTERS;
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break;
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#endif /* EFSYS_OPT_SIENA */
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default:
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rc = ENOTSUP;
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goto fail2;
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}
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enp->en_family = family;
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enp->en_esip = esip;
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enp->en_esbp = esbp;
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enp->en_eslp = eslp;
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*enpp = enp;
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return (0);
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fail2:
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EFSYS_PROBE(fail3);
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enp->en_magic = 0;
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/* Free the NIC object */
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EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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__checkReturn int
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efx_nic_probe(
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__in efx_nic_t *enp)
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{
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efx_nic_ops_t *enop;
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efx_oword_t oword;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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#if EFSYS_OPT_MCDI
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
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#endif /* EFSYS_OPT_MCDI */
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
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/* Test BIU */
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if ((rc = efx_nic_biu_test(enp)) != 0)
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goto fail1;
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/* Clear the region register */
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EFX_POPULATE_OWORD_4(oword,
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FRF_AZ_ADR_REGION0, 0,
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FRF_AZ_ADR_REGION1, (1 << 16),
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FRF_AZ_ADR_REGION2, (2 << 16),
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FRF_AZ_ADR_REGION3, (3 << 16));
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EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
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enop = enp->en_enop;
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if ((rc = enop->eno_probe(enp)) != 0)
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goto fail2;
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if ((rc = efx_phy_probe(enp)) != 0)
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goto fail3;
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enp->en_mod_flags |= EFX_MOD_PROBE;
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return (0);
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fail3:
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EFSYS_PROBE(fail3);
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enop->eno_unprobe(enp);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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#if EFSYS_OPT_PCIE_TUNE
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__checkReturn int
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efx_nic_pcie_tune(
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__in efx_nic_t *enp,
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unsigned int nlanes)
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{
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
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#if EFSYS_OPT_FALCON
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if (enp->en_family == EFX_FAMILY_FALCON)
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return (falcon_nic_pcie_tune(enp, nlanes));
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#endif
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return (ENOTSUP);
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}
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__checkReturn int
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efx_nic_pcie_extended_sync(
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__in efx_nic_t *enp)
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{
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
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#if EFSYS_OPT_SIENA
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if (enp->en_family == EFX_FAMILY_SIENA)
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return (siena_nic_pcie_extended_sync(enp));
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#endif
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return (ENOTSUP);
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}
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#endif /* EFSYS_OPT_PCIE_TUNE */
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__checkReturn int
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efx_nic_init(
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__in efx_nic_t *enp)
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{
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efx_nic_ops_t *enop = enp->en_enop;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
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if (enp->en_mod_flags & EFX_MOD_NIC) {
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rc = EINVAL;
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goto fail1;
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}
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if ((rc = enop->eno_init(enp)) != 0)
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goto fail2;
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enp->en_mod_flags |= EFX_MOD_NIC;
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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void
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efx_nic_fini(
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__in efx_nic_t *enp)
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{
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efx_nic_ops_t *enop = enp->en_enop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
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EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
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enop->eno_fini(enp);
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enp->en_mod_flags &= ~EFX_MOD_NIC;
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}
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void
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efx_nic_unprobe(
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__in efx_nic_t *enp)
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{
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efx_nic_ops_t *enop = enp->en_enop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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#if EFSYS_OPT_MCDI
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
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#endif /* EFSYS_OPT_MCDI */
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
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EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
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efx_phy_unprobe(enp);
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enop->eno_unprobe(enp);
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enp->en_mod_flags &= ~EFX_MOD_PROBE;
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}
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void
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efx_nic_destroy(
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__in efx_nic_t *enp)
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{
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efsys_identifier_t *esip = enp->en_esip;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
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enp->en_family = 0;
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enp->en_esip = NULL;
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enp->en_esbp = NULL;
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enp->en_eslp = NULL;
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enp->en_enop = NULL;
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enp->en_magic = 0;
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/* Free the NIC object */
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EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
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}
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__checkReturn int
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efx_nic_reset(
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__in efx_nic_t *enp)
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{
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efx_nic_ops_t *enop = enp->en_enop;
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|
unsigned int mod_flags;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
|
|
/*
|
|
* All modules except the MCDI, PROBE, NVRAM, VPD, MON (which we
|
|
* do not reset here) must have been shut down or never initialized.
|
|
*
|
|
* A rule of thumb here is: If the controller or MC reboots, is *any*
|
|
* state lost. If it's lost and needs reapplying, then the module
|
|
* *must* not be initialised during the reset.
|
|
*/
|
|
mod_flags = enp->en_mod_flags;
|
|
mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
|
|
EFX_MOD_VPD | EFX_MOD_MON);
|
|
EFSYS_ASSERT3U(mod_flags, ==, 0);
|
|
if (mod_flags != 0) {
|
|
rc = EINVAL;
|
|
goto fail1;
|
|
}
|
|
|
|
if ((rc = enop->eno_reset(enp)) != 0)
|
|
goto fail2;
|
|
|
|
enp->en_reset_flags |= EFX_RESET_MAC;
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
const efx_nic_cfg_t *
|
|
efx_nic_cfg_get(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
|
|
return (&(enp->en_nic_cfg));
|
|
}
|
|
|
|
#if EFSYS_OPT_DIAG
|
|
|
|
__checkReturn int
|
|
efx_nic_register_test(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_nic_ops_t *enop = enp->en_enop;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
|
|
EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
|
|
|
|
if ((rc = enop->eno_register_test(enp)) != 0)
|
|
goto fail1;
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_nic_test_registers(
|
|
__in efx_nic_t *enp,
|
|
__in efx_register_set_t *rsp,
|
|
__in size_t count)
|
|
{
|
|
unsigned int bit;
|
|
efx_oword_t original;
|
|
efx_oword_t reg;
|
|
efx_oword_t buf;
|
|
int rc;
|
|
|
|
while (count > 0) {
|
|
/* This function is only suitable for registers */
|
|
EFSYS_ASSERT(rsp->rows == 1);
|
|
|
|
/* bit sweep on and off */
|
|
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
|
|
B_TRUE);
|
|
for (bit = 0; bit < 128; bit++) {
|
|
/* Is this bit in the mask? */
|
|
if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
|
|
continue;
|
|
|
|
/* Test this bit can be set in isolation */
|
|
reg = original;
|
|
EFX_AND_OWORD(reg, rsp->mask);
|
|
EFX_SET_OWORD_BIT(reg, bit);
|
|
|
|
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
|
|
B_TRUE);
|
|
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
|
|
B_TRUE);
|
|
|
|
EFX_AND_OWORD(buf, rsp->mask);
|
|
if (memcmp(®, &buf, sizeof (reg))) {
|
|
rc = EIO;
|
|
goto fail1;
|
|
}
|
|
|
|
/* Test this bit can be cleared in isolation */
|
|
EFX_OR_OWORD(reg, rsp->mask);
|
|
EFX_CLEAR_OWORD_BIT(reg, bit);
|
|
|
|
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
|
|
B_TRUE);
|
|
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
|
|
B_TRUE);
|
|
|
|
EFX_AND_OWORD(buf, rsp->mask);
|
|
if (memcmp(®, &buf, sizeof (reg))) {
|
|
rc = EIO;
|
|
goto fail2;
|
|
}
|
|
}
|
|
|
|
/* Restore the old value */
|
|
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
|
|
B_TRUE);
|
|
|
|
--count;
|
|
++rsp;
|
|
}
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
/* Restore the old value */
|
|
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_nic_test_tables(
|
|
__in efx_nic_t *enp,
|
|
__in efx_register_set_t *rsp,
|
|
__in efx_pattern_type_t pattern,
|
|
__in size_t count)
|
|
{
|
|
efx_sram_pattern_fn_t func;
|
|
unsigned int index;
|
|
unsigned int address;
|
|
efx_oword_t reg;
|
|
efx_oword_t buf;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
|
|
func = __efx_sram_pattern_fns[pattern];
|
|
|
|
while (count > 0) {
|
|
/* Write */
|
|
address = rsp->address;
|
|
for (index = 0; index < rsp->rows; ++index) {
|
|
func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
|
|
func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
|
|
EFX_AND_OWORD(reg, rsp->mask);
|
|
EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
|
|
|
|
address += rsp->step;
|
|
}
|
|
|
|
/* Read */
|
|
address = rsp->address;
|
|
for (index = 0; index < rsp->rows; ++index) {
|
|
func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
|
|
func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
|
|
EFX_AND_OWORD(reg, rsp->mask);
|
|
EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
|
|
if (memcmp(®, &buf, sizeof (reg))) {
|
|
rc = EIO;
|
|
goto fail1;
|
|
}
|
|
|
|
address += rsp->step;
|
|
}
|
|
|
|
++rsp;
|
|
--count;
|
|
}
|
|
|
|
return (0);
|
|
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_DIAG */
|