f7a5c9d346
This is a MIPS4KC CPU with various embedded peripherals, including wireless and ethernet support. This commit includes the platform, UART, ethernet MAC and GPIO support. The interrupt-driven GPIO code is disabled for now pending GPIO changes from the submitter. Submitted by: Aleksandr Rybalko <ray@dlink.ua>
112 lines
4.4 KiB
C
112 lines
4.4 KiB
C
/*-
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* Copyright (c) 2010 Aleksandr Rybalko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _RT305X_GPIO_H_
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#define _RT305X_GPIO_H_
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#define NGPIO 52
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#define RGMII_GPIO_MODE_MASK (0x0fffULL<<40)
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#define SDRAM_GPIO_MODE_MASK (0xffffULL<<24)
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#define MDIO_GPIO_MODE_MASK (0x0003ULL<<22)
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#define JTAG_GPIO_MODE_MASK (0x001fULL<<17)
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#define UARTL_GPIO_MODE_MASK (0x0003ULL<<15)
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#define UARTF_GPIO_MODE_MASK (0x00ffULL<<7)
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#define SPI_GPIO_MODE_MASK (0x000fULL<<3)
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#define I2C_GPIO_MODE_MASK (0x0003ULL<<1)
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#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
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#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
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#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
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#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
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#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
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#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
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#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
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#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
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#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
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#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
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#define GPIO39_24_INT 0x38
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#define GPIO39_24_EDGE 0x3c
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#define GPIO39_24_RENA 0x40
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#define GPIO39_24_FENA 0x44
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#define GPIO39_24_DATA 0x48
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#define GPIO39_24_DIR 0x4c
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#define GPIO39_24_POL 0x50
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#define GPIO39_24_SET 0x54
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#define GPIO39_24_RESET 0x58
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#define GPIO39_24_TOG 0x5c
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#define GPIO51_40_INT 0x60
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#define GPIO51_40_EDGE 0x64
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#define GPIO51_40_RENA 0x68
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#define GPIO51_40_FENA 0x6C
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#define GPIO51_40_DATA 0x70
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#define GPIO51_40_DIR 0x74
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#define GPIO51_40_POL 0x78
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#define GPIO51_40_SET 0x7C
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#define GPIO51_40_RESET 0x80
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#define GPIO51_40_TOG 0x84
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#define GPIO_REG(g, n) \
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((g<24)?(GPIO23_00_##n):(g<40)?(GPIO39_24_##n):(GPIO51_40_##n))
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#define GPIO_MASK(g) \
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((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40)))
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#define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40))
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#define GPIO_READ(r, g, n) \
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bus_read_4(r->gpio_mem_res, GPIO_REG(g, n))
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#define GPIO_WRITE(r, g, n, v) \
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bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v)
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#define GPIO_READ_ALL(r, n) \
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(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) | \
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(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\
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(((uint64_t)bus_read_4(r->gpio_mem_res, GPIO51_40_##n)) << 40))
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#define GPIO_WRITE_ALL(r, n, v) \
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{bus_write_4(r->gpio_mem_res,GPIO23_00_##n, v &0x00ffffff);\
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bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\
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bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);}
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#define GPIO_BIT_CLR(r, g, n) \
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bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
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bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) & ~GPIO_MASK(g))
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#define GPIO_BIT_SET(r, g, n) \
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bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \
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bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g))
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#define GPIO_BIT_GET(r, g, n) \
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((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \
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GPIO_BIT_SHIFT(g)) & 1)
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
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#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
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#endif /* _RT305X_GPIO_H_ */
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