4d0abc074b
On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_BOARD_H__
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#define __NLM_BOARD_H__
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#define XLP_NAE_NBLOCKS 5
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#define XLP_NAE_NPORTS 4
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#define XLP_I2C_MAXDEVICES 8
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/*
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* EVP board EEPROM info
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*/
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#define EEPROM_I2CBUS 1
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#define EEPROM_I2CADDR 0xAE
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#define EEPROM_SIZE 48
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#define EEPROM_MACADDR_OFFSET 2
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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struct xlp_port_ivars {
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int port;
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int block;
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int type;
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int phy_addr;
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};
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struct xlp_block_ivars {
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int block;
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int type;
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u_int portmask;
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struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS];
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};
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struct xlp_nae_ivars {
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int node;
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u_int blockmask;
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struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
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};
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struct xlp_board_info {
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u_int nodemask;
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struct xlp_node_info {
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struct xlp_nae_ivars nae_ivars;
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} nodes[XLP_MAX_NODES];
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};
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int nlm_board_info_setup(void);
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int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
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uint8_t *buf,int sz);
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uint64_t nlm_board_cpld_base(int node, int chipselect);
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int nlm_board_cpld_majorversion(uint64_t cpldbase);
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int nlm_board_cpld_minorversion(uint64_t cpldbase);
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void nlm_board_cpld_reset(uint64_t cpldbase);
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int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
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#endif
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#endif
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