4d88d6566a
- It actually works this time, honest!
- Fine grained TLB shootdowns for SMP on i386. IPI's are very expensive,
so try and optimize things where possible.
- Introduce ranged shootdowns that can be done as a single IPI.
- PG_G support for i386
- Specific-cpu targeted shootdowns. For example, there is no sense in
globally purging the TLB cache for where we are stealing a page from
the local unshared process on the local cpu. Use pm_active to track
this.
- Add some instrumentation for the tlb shootdown code.
- Rip out SMP code from <machine/cpufunc.h>
- Try and fix some very bogus PG_G and PG_PS interactions that were bad
enough to cause vm86 bios calls to break. vm86 depended on our existing
bugs and this was the cause of the VESA panics last time.
- Fix the silly one-line error that caused the 'panic: bad pte' last time.
- Fix a couple of other silly one-line errors that should have caused more
pain than they did.
Some more work is needed:
- pmap_{zero,copy}_page[_idle]. These can be done without IPI's if we
have a hook in cpu_switch.
- The IPI handlers need some cleanup. I have a bogus %ds load that can
be avoided.
- APTD handling is rather bogus and appears to be a large source of
global TLB IPI shootdowns for no really good reason.
I see speedups of between 1.5% and ~4% on buildworlds in a while 1 loop.
I expect to see a bigger difference when there is significant pageout
activity or the system otherwise has memory shortages.
I have backed out a few optimizations that I had been using over the last
few days in order to be a little more conservative. I'll revisit these
again over the next few days as the dust settles.
New option: DISABLE_PG_G - In case I missed something.
672 lines
14 KiB
C
672 lines
14 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Functions to provide access to special i386 instructions.
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* This in included in sys/systm.h, and that file should be
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* used in preference to this.
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#include <sys/cdefs.h>
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#include <machine/psl.h>
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struct thread;
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__BEGIN_DECLS
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#define readb(va) (*(volatile u_int8_t *) (va))
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#define readw(va) (*(volatile u_int16_t *) (va))
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#define readl(va) (*(volatile u_int32_t *) (va))
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#define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
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#define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
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#define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
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#ifdef __GNUC__
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#ifdef SWTCH_OPTIM_STATS
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extern int tlb_flush_count; /* XXX */
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#endif
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("int $3");
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}
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static __inline u_int
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bsfl(u_int mask)
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{
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u_int result;
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__asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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static __inline u_int
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bsrl(u_int mask)
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{
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u_int result;
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__asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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static __inline void
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disable_intr(void)
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{
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__asm __volatile("cli" : : : "memory");
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}
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static __inline void
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do_cpuid(u_int ax, u_int *p)
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{
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__asm __volatile("cpuid"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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}
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static __inline void
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enable_intr(void)
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{
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__asm __volatile("sti");
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}
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#define HAVE_INLINE_FFS
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static __inline int
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ffs(int mask)
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{
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/*
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* Note that gcc-2's builtin ffs would be used if we didn't declare
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* this inline or turn off the builtin. The builtin is faster but
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* broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
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* versions.
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*/
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return (mask == 0 ? mask : bsfl((u_int)mask) + 1);
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}
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#define HAVE_INLINE_FLS
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static __inline int
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fls(int mask)
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{
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return (mask == 0 ? mask : bsrl((u_int)mask) + 1);
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}
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#if __GNUC__ < 2
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#define inb(port) inbv(port)
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#define outb(port, data) outbv(port, data)
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#else /* __GNUC >= 2 */
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/*
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* The following complications are to get around gcc not having a
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* constraint letter for the range 0..255. We still put "d" in the
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* constraint because "i" isn't a valid constraint when the port
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* isn't constant. This only matters for -O0 because otherwise
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* the non-working version gets optimized away.
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*
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* Use an expression-statement instead of a conditional expression
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* because gcc-2.6.0 would promote the operands of the conditional
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* and produce poor code for "if ((inb(var) & const1) == const2)".
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*
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* The unnecessary test `(port) < 0x10000' is to generate a warning if
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* the `port' has type u_short or smaller. Such types are pessimal.
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* This actually only works for signed types. The range check is
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* careful to avoid generating warnings.
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*/
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#define inb(port) __extension__ ({ \
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u_char _data; \
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if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
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&& (port) < 0x10000) \
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_data = inbc(port); \
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else \
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_data = inbv(port); \
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_data; })
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#define outb(port, data) ( \
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__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
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&& (port) < 0x10000 \
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? outbc(port, data) : outbv(port, data))
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static __inline u_char
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inbc(u_int port)
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{
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u_char data;
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__asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
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return (data);
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}
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static __inline void
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outbc(u_int port, u_char data)
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{
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__asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
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}
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#endif /* __GNUC <= 2 */
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static __inline u_char
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inbv(u_int port)
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{
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u_char data;
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/*
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* We use %%dx and not %1 here because i/o is done at %dx and not at
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* %edx, while gcc generates inferior code (movw instead of movl)
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* if we tell it to load (u_short) port.
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*/
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__asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline u_int
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inl(u_int port)
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{
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u_int data;
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__asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline void
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insb(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insb"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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}
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static __inline void
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insw(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insw"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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}
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static __inline void
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insl(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insl"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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}
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static __inline void
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invd(void)
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{
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__asm __volatile("invd");
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}
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static __inline u_short
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inw(u_int port)
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{
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u_short data;
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__asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline void
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outbv(u_int port, u_char data)
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{
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u_char al;
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/*
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* Use an unnecessary assignment to help gcc's register allocator.
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* This make a large difference for gcc-1.40 and a tiny difference
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* for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
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* best results. gcc-2.6.0 can't handle this.
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*/
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al = data;
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__asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
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}
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static __inline void
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outl(u_int port, u_int data)
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{
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/*
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* outl() and outw() aren't used much so we haven't looked at
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* possible micro-optimizations such as the unnecessary
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* assignment for them.
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*/
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__asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
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}
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static __inline void
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outsb(u_int port, const void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsb"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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}
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static __inline void
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outsw(u_int port, const void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsw"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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}
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static __inline void
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outsl(u_int port, const void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsl"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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}
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static __inline void
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outw(u_int port, u_short data)
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{
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__asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
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}
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static __inline void
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ia32_pause(void)
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{
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__asm __volatile("pause");
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}
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static __inline u_int
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read_eflags(void)
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{
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u_int ef;
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__asm __volatile("pushfl; popl %0" : "=r" (ef));
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return (ef);
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}
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static __inline u_int64_t
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rdmsr(u_int msr)
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{
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u_int64_t rv;
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__asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
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return (rv);
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}
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static __inline u_int64_t
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rdpmc(u_int pmc)
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{
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u_int64_t rv;
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__asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
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return (rv);
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}
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static __inline u_int64_t
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rdtsc(void)
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{
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u_int64_t rv;
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__asm __volatile("rdtsc" : "=A" (rv));
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return (rv);
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}
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static __inline void
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wbinvd(void)
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{
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__asm __volatile("wbinvd");
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}
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static __inline void
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write_eflags(u_int ef)
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{
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__asm __volatile("pushl %0; popfl" : : "r" (ef));
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}
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static __inline void
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wrmsr(u_int msr, u_int64_t newval)
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{
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__asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
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}
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static __inline void
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load_cr0(u_int data)
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{
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__asm __volatile("movl %0,%%cr0" : : "r" (data));
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}
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static __inline u_int
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rcr0(void)
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{
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u_int data;
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__asm __volatile("movl %%cr0,%0" : "=r" (data));
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return (data);
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}
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static __inline u_int
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rcr2(void)
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{
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u_int data;
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__asm __volatile("movl %%cr2,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_cr3(u_int data)
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{
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__asm __volatile("movl %0,%%cr3" : : "r" (data) : "memory");
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#if defined(SWTCH_OPTIM_STATS)
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++tlb_flush_count;
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#endif
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}
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static __inline u_int
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rcr3(void)
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{
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u_int data;
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__asm __volatile("movl %%cr3,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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load_cr4(u_int data)
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{
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__asm __volatile("movl %0,%%cr4" : : "r" (data));
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}
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static __inline u_int
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rcr4(void)
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{
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u_int data;
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__asm __volatile("movl %%cr4,%0" : "=r" (data));
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return (data);
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}
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/*
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* Global TLB flush (except for thise for pages marked PG_G)
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*/
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static __inline void
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invltlb(void)
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{
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load_cr3(rcr3());
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}
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|
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/*
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* TLB flush for an individual page (even if it has PG_G).
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* Only works on 486+ CPUs (i386 does not have PG_G).
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*/
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static __inline void
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invlpg(u_int addr)
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{
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__asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
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}
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static __inline u_int
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rfs(void)
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{
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u_int sel;
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__asm __volatile("movl %%fs,%0" : "=rm" (sel));
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return (sel);
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}
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static __inline u_int
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rgs(void)
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{
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u_int sel;
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__asm __volatile("movl %%gs,%0" : "=rm" (sel));
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return (sel);
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}
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static __inline void
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load_fs(u_int sel)
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{
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__asm __volatile("movl %0,%%fs" : : "rm" (sel));
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}
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static __inline void
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load_gs(u_int sel)
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{
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__asm __volatile("movl %0,%%gs" : : "rm" (sel));
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}
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static __inline u_int
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rdr0(void)
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|
{
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u_int data;
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__asm __volatile("movl %%dr0,%0" : "=r" (data));
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|
return (data);
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}
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static __inline void
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load_dr0(u_int dr0)
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{
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__asm __volatile("movl %0,%%dr0" : : "r" (dr0));
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}
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static __inline u_int
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rdr1(void)
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|
{
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|
u_int data;
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|
__asm __volatile("movl %%dr1,%0" : "=r" (data));
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return (data);
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}
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static __inline void
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|
load_dr1(u_int dr1)
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{
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|
__asm __volatile("movl %0,%%dr1" : : "r" (dr1));
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}
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static __inline u_int
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rdr2(void)
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|
{
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|
u_int data;
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|
__asm __volatile("movl %%dr2,%0" : "=r" (data));
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|
return (data);
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}
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static __inline void
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load_dr2(u_int dr2)
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|
{
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|
__asm __volatile("movl %0,%%dr2" : : "r" (dr2));
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|
}
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static __inline u_int
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|
rdr3(void)
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|
{
|
|
u_int data;
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|
__asm __volatile("movl %%dr3,%0" : "=r" (data));
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|
return (data);
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|
}
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static __inline void
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|
load_dr3(u_int dr3)
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|
{
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|
__asm __volatile("movl %0,%%dr3" : : "r" (dr3));
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|
}
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static __inline u_int
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rdr4(void)
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|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr4,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr4(u_int dr4)
|
|
{
|
|
__asm __volatile("movl %0,%%dr4" : : "r" (dr4));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr5(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr5,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr5(u_int dr5)
|
|
{
|
|
__asm __volatile("movl %0,%%dr5" : : "r" (dr5));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr6(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr6,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr6(u_int dr6)
|
|
{
|
|
__asm __volatile("movl %0,%%dr6" : : "r" (dr6));
|
|
}
|
|
|
|
static __inline u_int
|
|
rdr7(void)
|
|
{
|
|
u_int data;
|
|
__asm __volatile("movl %%dr7,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr7(u_int dr7)
|
|
{
|
|
__asm __volatile("movl %0,%%dr7" : : "r" (dr7));
|
|
}
|
|
|
|
static __inline register_t
|
|
intr_disable(void)
|
|
{
|
|
register_t eflags;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
return (eflags);
|
|
}
|
|
|
|
static __inline void
|
|
intr_restore(register_t eflags)
|
|
{
|
|
write_eflags(eflags);
|
|
}
|
|
|
|
#else /* !__GNUC__ */
|
|
|
|
int breakpoint(void);
|
|
u_int bsfl(u_int mask);
|
|
u_int bsrl(u_int mask);
|
|
void cpu_invlpg(u_int addr);
|
|
void cpu_invlpg_range(u_int start, u_int end);
|
|
void disable_intr(void);
|
|
void do_cpuid(u_int ax, u_int *p);
|
|
void enable_intr(void);
|
|
u_char inb(u_int port);
|
|
u_int inl(u_int port);
|
|
void insb(u_int port, void *addr, size_t cnt);
|
|
void insl(u_int port, void *addr, size_t cnt);
|
|
void insw(u_int port, void *addr, size_t cnt);
|
|
void invd(void);
|
|
void invlpg(u_int addr);
|
|
void invlpg_range(u_int start, u_int end);
|
|
void invltlb(void);
|
|
u_short inw(u_int port);
|
|
void load_cr0(u_int cr0);
|
|
void load_cr3(u_int cr3);
|
|
void load_cr4(u_int cr4);
|
|
void load_fs(u_int sel);
|
|
void load_gs(u_int sel);
|
|
void outb(u_int port, u_char data);
|
|
void outl(u_int port, u_int data);
|
|
void outsb(u_int port, void *addr, size_t cnt);
|
|
void outsl(u_int port, void *addr, size_t cnt);
|
|
void outsw(u_int port, void *addr, size_t cnt);
|
|
void outw(u_int port, u_short data);
|
|
void ia32_pause(void);
|
|
u_int rcr0(void);
|
|
u_int rcr2(void);
|
|
u_int rcr3(void);
|
|
u_int rcr4(void);
|
|
u_int rfs(void);
|
|
u_int rgs(void);
|
|
u_int64_t rdmsr(u_int msr);
|
|
u_int64_t rdpmc(u_int pmc);
|
|
u_int64_t rdtsc(void);
|
|
u_int read_eflags(void);
|
|
void wbinvd(void);
|
|
void write_eflags(u_int ef);
|
|
void wrmsr(u_int msr, u_int64_t newval);
|
|
u_int rdr0(void);
|
|
void load_dr0(u_int dr0);
|
|
u_int rdr1(void);
|
|
void load_dr1(u_int dr1);
|
|
u_int rdr2(void);
|
|
void load_dr2(u_int dr2);
|
|
u_int rdr3(void);
|
|
void load_dr3(u_int dr3);
|
|
u_int rdr4(void);
|
|
void load_dr4(u_int dr4);
|
|
u_int rdr5(void);
|
|
void load_dr5(u_int dr5);
|
|
u_int rdr6(void);
|
|
void load_dr6(u_int dr6);
|
|
u_int rdr7(void);
|
|
void load_dr7(u_int dr7);
|
|
register_t intr_disable(void);
|
|
void intr_restore(register_t ef);
|
|
|
|
#endif /* __GNUC__ */
|
|
|
|
void ltr(u_short sel);
|
|
void reset_dbregs(void);
|
|
|
|
__END_DECLS
|
|
|
|
#endif /* !_MACHINE_CPUFUNC_H_ */
|