dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
235 lines
7.4 KiB
C
235 lines
7.4 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Source file for the zip (deflate) block
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*
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* <hr>$Revision: 70030 $<hr>
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*/
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#include "executive-config.h"
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-cmd-queue.h"
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#include "cvmx-zip.h"
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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/**
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* Initialize the ZIP block
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_initialize(void)
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{
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cvmx_zip_cmd_buf_t zip_cmd_buf;
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cvmx_cmd_queue_result_t result;
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result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_ZIP, 0,
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CVMX_FPA_OUTPUT_BUFFER_POOL,
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CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
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if (result != CVMX_CMD_QUEUE_SUCCESS)
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return -1;
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zip_cmd_buf.u64 = 0;
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zip_cmd_buf.s.dwb = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
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zip_cmd_buf.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
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zip_cmd_buf.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
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zip_cmd_buf.s.ptr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_ZIP))>>7;
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cvmx_write_csr(CVMX_ZIP_CMD_BUF, zip_cmd_buf.u64);
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cvmx_write_csr(CVMX_ZIP_ERROR, 1);
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cvmx_read_csr(CVMX_ZIP_CMD_BUF); /* Read to make sure setup is complete */
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return 0;
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}
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/**
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* Initialize the ZIP QUEUE buffer
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*
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* @param queue : ZIP instruction queue
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* @param zcoremask : ZIP coremask to use for this queue
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_queue_initialize(int queue, int zcoremask)
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{
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cvmx_zip_quex_buf_t zip_que_buf;
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cvmx_cmd_queue_result_t result;
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cvmx_zip_quex_map_t que_map;
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cvmx_zip_que_ena_t que_ena;
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cvmx_zip_int_reg_t int_reg;
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/* Previous Octeon models has only one instruction queue, call
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cvmx_zip_inititalize() to initialize the ZIP block */
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if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
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return -1;
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result = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_ZIP_QUE(queue), 0,
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CVMX_FPA_OUTPUT_BUFFER_POOL,
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CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE);
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if (result != CVMX_CMD_QUEUE_SUCCESS)
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return -1;
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/* 1. Program ZIP_QUE0/1_BUF to have the correct buffer pointer and
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size configured for each instruction queue */
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zip_que_buf.u64 = 0;
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zip_que_buf.s.dwb = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/128;
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zip_que_buf.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
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zip_que_buf.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE/8;
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zip_que_buf.s.ptr = cvmx_ptr_to_phys(cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_ZIP_QUE(queue)))>>7;
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cvmx_write_csr(CVMX_ZIP_QUEX_BUF(queue), zip_que_buf.u64);
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/* 2. Change the queue-to-ZIP core mapping by programming ZIP_QUE0/1_MAP. */
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que_map.u64 = cvmx_read_csr(CVMX_ZIP_QUEX_MAP(queue));
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que_map.s.zce = zcoremask;
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cvmx_write_csr(CVMX_ZIP_QUEX_MAP(queue), que_map.u64);
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/* Enable the queue */
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que_ena.u64 = cvmx_read_csr(CVMX_ZIP_QUE_ENA);
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que_ena.s.ena |= (1<<queue);
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cvmx_write_csr(CVMX_ZIP_QUE_ENA, que_ena.u64);
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/* Use round robin to have equal priority for each instruction queue */
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cvmx_write_csr(CVMX_ZIP_QUE_PRI, 0x3);
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int_reg.u64 = cvmx_read_csr(CVMX_ZIP_INT_REG);
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if (queue)
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int_reg.s.doorbell1 = 1;
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else
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int_reg.s.doorbell0 = 1;
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cvmx_write_csr(CVMX_ZIP_INT_REG, int_reg.u64);
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/* Read back to make sure the setup is complete */
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cvmx_read_csr(CVMX_ZIP_QUEX_BUF(queue));
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return 0;
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}
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/**
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* Shutdown the ZIP block. ZIP must be idle when
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* this function is called.
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_shutdown(void)
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{
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cvmx_zip_cmd_ctl_t zip_cmd_ctl;
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if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_ZIP))
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{
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cvmx_dprintf("ERROR: cvmx_zip_shutdown: ZIP not idle.\n");
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return -1;
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}
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zip_cmd_ctl.u64 = cvmx_read_csr(CVMX_ZIP_CMD_CTL);
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zip_cmd_ctl.s.reset = 1;
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cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64);
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cvmx_wait(100);
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cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_ZIP);
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return 0;
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}
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/**
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* Shutdown the ZIP block for a queue. ZIP must be idle when
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* this function is called.
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*
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* @param queue Zip instruction queue of the command
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_queue_shutdown(int queue)
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{
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cvmx_zip_cmd_ctl_t zip_cmd_ctl;
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if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_ZIP_QUE(queue)))
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{
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cvmx_dprintf("ERROR: cvmx_zip_shutdown: ZIP not idle.\n");
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return -1;
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}
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zip_cmd_ctl.u64 = cvmx_read_csr(CVMX_ZIP_CMD_CTL);
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zip_cmd_ctl.s.reset = 1;
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cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64);
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cvmx_wait(100);
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cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_ZIP_QUE(queue));
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return 0;
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}
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/**
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* Submit a command to the ZIP block
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*
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* @param command Zip command to submit
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_submit(cvmx_zip_command_t *command)
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{
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cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_ZIP, 1, 8, command->u64);
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if (result == CVMX_CMD_QUEUE_SUCCESS)
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cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(7, 0)), 8);
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return result;
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}
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/**
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* Submit a command to the ZIP block
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*
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* @param command Zip command to submit
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* @param queue Zip instruction queue of the command
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_zip_queue_submit(cvmx_zip_command_t *command, int queue)
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{
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cvmx_cmd_queue_result_t result = cvmx_cmd_queue_write(CVMX_CMD_QUEUE_ZIP_QUE(queue), 1, 8, command->u64);
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if (result == CVMX_CMD_QUEUE_SUCCESS)
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cvmx_write_csr((CVMX_ADDR_DID(CVMX_FULL_DID(7, 0)) | queue << 3), 8);
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return result;
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}
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#endif
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