mw 3d41e80ced Enable UART support for Xilinx Ultrascale+ SoCs ... Xilinx Ultrascale+ are based on Cortex-A53 and use existing UART driver (uart_dev_cdnc). Enable it in arm64 GENERIC config. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf		2018-07-13 19:54:22 +00:00
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files.zynq7	o Move sdhci_fdt to the generic files list.	2018-01-25 17:16:29 +00:00
std.zynq7	Make kernel option KERNVIRTADDR optional, remove it from std.<platform>	2017-12-30 00:20:49 +00:00
uart_dev_cdnc.c	Enable UART support for Xilinx Ultrascale+ SoCs	2018-07-13 19:54:22 +00:00
zy7_devcfg.c	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00
zy7_ehci.c	arm: Fix duplicate ehci DRIVER_MODULE	2018-04-27 21:05:58 +00:00
zy7_gpio.c	Fix accidental USB port resets by GPIO on Zynq/Zedboard boards	2018-04-03 04:31:54 +00:00
zy7_l2cache.c	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00
zy7_machdep.c	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00
zy7_machdep.h
zy7_mp.c
zy7_reg.h	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00
zy7_slcr.c	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00
zy7_slcr.h	sys/arm: further adoption of SPDX licensing ID tags.	2017-11-27 15:04:10 +00:00