0648f71275
bugs related to support of dc21041 chips and other problems. Submitted by: Matt Thomas <matt@3am-software.com>
421 lines
18 KiB
C
421 lines
18 KiB
C
/*-
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* Copyright (c) 1994, 1995 Matt Thomas (thomas@lkg.dec.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software withough specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: dc21040.h,v 1.4.4.1 1995/10/01 06:03:59 davidg Exp $
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*
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*/
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#if !defined(_DC21040_H)
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#define _DC21040_H
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typedef unsigned short tulip_uint16_t;
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typedef unsigned int tulip_uint32_t;
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#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
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#define TULIP_BITFIELD2(a, b) b, a
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#define TULIP_BITFIELD3(a, b, c) c, b, a
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#define TULIP_BITFIELD4(a, b, c, d) d, c, b, a
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#else
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#define TULIP_BITFIELD2(a, b) a, b
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#define TULIP_BITFIELD3(a, b, c) a, b, c
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#define TULIP_BITFIELD4(a, b, c, d) a, b, c, d
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#endif
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typedef struct {
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tulip_uint32_t d_status;
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tulip_uint32_t TULIP_BITFIELD3(d_length1 : 11,
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d_length2 : 11,
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d_flag : 10);
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tulip_uint32_t d_addr1;
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tulip_uint32_t d_addr2;
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} tulip_desc_t;
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#define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = DC21040) */
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#define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */
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/*
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* Transmit Status
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*/
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#define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */
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#define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */
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#define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */
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#define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */
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#define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */
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#define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */
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#define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */
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#define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */
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#define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */
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#define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */
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#define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */
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/*
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* Receive Status
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*/
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#define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */
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#define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */
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#define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */
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#define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */
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#define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */
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#define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */
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#define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */
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#define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */
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#define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */
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#define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */
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#define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */
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#define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */
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#define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */
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#define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */
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#define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */
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#define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */
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#define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */
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#define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */
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#define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */
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#define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */
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#define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */
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#define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */
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#define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */
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/*
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* The DC21040 Registers (IO Space Addresses)
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*/
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#define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */
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#define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */
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#define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */
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#define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */
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#define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */
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#define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */
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#define TULIP_REG_CMD 0x30 /* CSR6 -- Command */
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#define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */
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#define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */
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#define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */
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#define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */
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#define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */
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#define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */
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#define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */
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#define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */
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#define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */
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/*
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* CSR5 -- Status Register
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* CSR7 -- Interrupt Control
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*/
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#define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */
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#define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */
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#define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */
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#define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */
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#define TULIP_STS_ERR_SHIFT 23
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#define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */
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#define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */
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#define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */
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#define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */
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#define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */
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#define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */
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#define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */
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#define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an
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unavailable transmit descriptor */
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#define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */
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#define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/
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#define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */
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#define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */
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#define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive
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packet before prefetch of next descriptor */
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#define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */
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#define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of
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unavailable receive buffers */
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#define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */
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#define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame
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from the receive FIFO as a result of
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an unavailable receive buffer */
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#define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame
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from the receive FIFO into the receive
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buffer. */
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#define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */
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#define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */
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#define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */
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#define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (DC21040) */
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#define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (DC21040) */
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#define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (DC21140) */
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#define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (DC21040) */
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#define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */
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#define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */
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#define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */
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#define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */
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#define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */
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#define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (DC21041) */
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#define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */
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#define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */
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#define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */
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#define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */
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/*
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* CSR6 -- Command (Operation Mode) Register
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*/
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#define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (DC21140) */
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#define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (DC21140) */
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#define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (DC21140) */
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#define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (DC21140) */
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#define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (DC21140) */
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#define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (DC21140) */
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#define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (DC21140) */
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#define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (DC21041) */
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#define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */
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#define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (DC21040) */
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#define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */
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#define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */
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#define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */
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#define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */
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#define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */
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#define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */
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#define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */
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#define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
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#define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
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#define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */
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#define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */
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#define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */
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#define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */
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#define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */
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#define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */
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#define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */
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#define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */
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#define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */
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#define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L
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#define TULIP_SIASTS_RXACTIVITY 0x00000100L
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#define TULIP_SIASTS_LINKFAIL 0x00000004L
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#define TULIP_SIACONN_RESET 0x00000000L
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#define TULIP_SIACONN_AUI 0x0000000DL
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#define TULIP_SIACONN_10BASET 0x00000005L
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#define TULIP_DC21041_SIACONN_10BASET 0x0000EF01L
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#define TULIP_DC21041_SIATXRX_10BASET 0x0000FF3FL
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#define TULIP_DC21041_SIATXRX_10BASET_FD 0x0000FF3DL
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#define TULIP_DC21041_SIAGEN_10BASET 0x00000000L
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#define TULIP_DC21041_SIACONN_AUI 0x0000EF09L
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#define TULIP_DC21041_SIATXRX_AUI 0x0000F73DL
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#define TULIP_DC21041_SIAGEN_AUI 0x0000000EL
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#define TULIP_DC21041_SIACONN_BNC 0x0000EF09L
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#define TULIP_DC21041_SIATXRX_BNC 0x0000F73DL
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#define TULIP_DC21041_SIAGEN_BNC 0x00000006L
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#define TULIP_WATCHDOG_TXDISABLE 0x00000001L
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#define TULIP_WATCHDOG_RXDISABLE 0x00000010L
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#define TULIP_BUSMODE_SWRESET 0x00000001L
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#define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL
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#define TULIP_BUSMODE_BIGENDIAN 0x00000080L
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#define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L
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#define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L
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#define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L
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#define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L
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#define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L
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#define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L
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#define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L
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#define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L
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#define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L
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#define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L
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#define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L
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#define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L
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#define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L
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#define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L
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#define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L
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#define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L
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#define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* DC21041 only */
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#define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* DC21041 only */
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#define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* DC21041 only */
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#define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* DC21041 only */
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#define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* DC21041 only */
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#define TULIP_REG_CFDA 0x40
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#define TULIP_CFDA_SLEEP 0x80000000L
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#define TULIP_CFDA_SNOOZE 0x40000000L
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/*
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* These are the defintitions used for the DEC DC21140
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* evaluation board.
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*/
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#define TULIP_GP_EB_PINS 0x0000011F /* General Purpose Pin directions */
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#define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
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#define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
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#define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */
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/*
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* These are the defintitions used for the SMC9332 (DC21140) board.
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*/
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#define TULIP_GP_SMC_9332_PINS 0x0000013F /* General Purpose Pin directions */
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#define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
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#define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
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#define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */
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#define TULIP_OUI_SMC_0 0x00
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#define TULIP_OUI_SMC_1 0x00
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#define TULIP_OUI_SMC_2 0xC0
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/*
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* There are the definitions used for the DEC DE500
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* 10/100 family of boards
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*/
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#define TULIP_GP_DE500_PINS 0x0000011FL
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#define TULIP_GP_DE500_LINK_PASS 0x00000080L
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#define TULIP_GP_DE500_SYM_LINK 0x00000040L
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#define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L
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#define TULIP_GP_DE500_PHY_RESET 0x00000010L
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#define TULIP_GP_DE500_HALFDUPLEX 0x00000008L
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#define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L
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#define TULIP_GP_DE500_FORCE_LED 0x00000002L
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#define TULIP_GP_DE500_FORCE_100 0x00000001L
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/*
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* These are the defintitions used for the Cogent EM100
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* DC21140 board.
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*/
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#define TULIP_GP_EM100_PINS 0x0000013F /* General Purpose Pin directions */
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#define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */
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#define TULIP_OUI_COGENT_0 0x00
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#define TULIP_OUI_COGENT_1 0x00
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#define TULIP_OUI_COGENT_2 0x92
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#define TULIP_COGENT_EM100_ID 0x12
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/*
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* These are the defintitions used for the Znyx ZX342
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* 10/100 board
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*/
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#define TULIP_GP_ZX34X_PINS 0x0000011F /* General Purpose Pin directions */
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#define TULIP_GP_ZX34X_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
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#define TULIP_GP_ZX34X_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
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#define TULIP_GP_ZX34X_INIT 0x00000009
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#define TULIP_OUI_ZNYX_0 0x00
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#define TULIP_OUI_ZNYX_1 0xC0
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#define TULIP_OUI_ZNYX_2 0x95
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/*
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* Compex's OUI. We need to twiddle a bit on their DC21041 card.
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*/
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#define TULIP_OUI_COMPEX_0 0x00
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#define TULIP_OUI_COMPEX_1 0x80
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#define TULIP_OUI_COMPEX_2 0x48
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#define TULIP_DC21041_COMPEX_XREGDATA 1
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/*
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* SROM definitions for the DC21140 and DC21041.
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*/
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#define SROMXREG 0x0400
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#define SROMSEL 0x0800
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#define SROMRD 0x4000
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#define SROMWR 0x2000
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#define SROMDIN 0x0008
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#define SROMDOUT 0x0004
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#define SROMDOUTON 0x0004
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#define SROMDOUTOFF 0x0004
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#define SROMCLKON 0x0002
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#define SROMCLKOFF 0x0002
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#define SROMCSON 0x0001
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#define SROMCSOFF 0x0001
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#define SROMCS 0x0001
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#define SROMCMD_MODE 4
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#define SROMCMD_WR 5
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#define SROMCMD_RD 6
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#define SROM_BITWIDTH 6
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/*
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* MII Definitions for the DC21041 and DC21140/DC21140A/DC21142
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*/
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#define MII_PREAMBLE (~0)
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#define MII_TEST 0xAAAAAAAA
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#define MII_RDCMD 0xF6 /* 1111.0110 */
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#define MII_WRCMD 0xF5 /* 1111.0101 */
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#define MII_DIN 0x00080000
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#define MII_RD 0x00040000
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#define MII_WR 0x00000000
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#define MII_DOUT 0x00020000
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#define MII_CLK 0x00010000
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#define MII_CLKON MII_CLK
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#define MII_CLKOFF MII_CLK
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#define PHYREG_CONTROL 0
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#define PHYREG_STATUS 1
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#define PHYREG_IDLOW 2
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#define PHYREG_IDHIGH 3
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#define PHYREG_AUTONEG_ADVERTISEMENT 4
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#define PHYREG_AUTONEG_ABILITIES 5
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#define PHYREG_AUTONEG_EXPANSION 6
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#define PHYREG_AUTONEG_NEXTPAGE 7
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#define PHYSTS_100BASET4 0x8000
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#define PHYSTS_100BASETX_FD 0x4000
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#define PHYSTS_100BASETX 0x2000
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#define PHYSTS_10BASET_FD 0x1000
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#define PHYSTS_10BASET 0x0800
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#define PHYSTS_AUTONEG_DONE 0x0020
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#define PHYSTS_REMOTE_FAULT 0x0010
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#define PHYSTS_CAN_AUTONEG 0x0008
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#define PHYSTS_LINK_UP 0x0004
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#define PHYSTS_JABBER_DETECT 0x0002
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#define PHYSTS_EXTENDED_REGS 0x0001
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#define PHYCTL_RESET 0x8000
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#define PHYCTL_SELECT_100MB 0x2000
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#define PHYCTL_AUTONEG_ENABLE 0x1000
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#define PHYCTL_ISOLATE 0x0400
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#define PHYCTL_AUTONEG_RESTART 0x0200
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#define PHYCTL_FULL_DUPLEX 0x0100
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#define MII_RD 0x00040000
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#define MII_WR 0x00000000
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#define MII_DIN 0x00080000
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#define MII_DOUT 0x00020000
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#define MII_DOUTON MII_DOUT
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#define MII_DOUTOFF MII_DOUT
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#define MII_CLK 0x00010000
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#define MII_CLKON MII_CLK
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#define MII_CLKOFF MII_CLK
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/*
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* Definitions for the DE425.
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*/
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#define DE425_CFID 0x08 /* Configuration Id */
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#define DE425_CFCS 0x0C /* Configuration Command-Status */
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#define DE425_CFRV 0x18 /* Configuration Revision */
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#define DE425_CFLT 0x1C /* Configuration Latency Timer */
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#define DE425_CBIO 0x28 /* Configuration Base IO Address */
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#define DE425_CFDA 0x2C /* Configuration Driver Area */
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#define DE425_ENETROM_OFFSET 0xC90 /* Offset in I/O space for ENETROM */
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#define DE425_CFG0 0xC88 /* IRQ register */
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#define DE425_EISAID 0x10a34250 /* EISA device id */
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#define DE425_EISA_IOSIZE 0x100
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#define DEC_VENDORID 0x1011
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#define DC21040_CHIPID 0x0002
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#define DC21140_CHIPID 0x0009
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#define DC21041_CHIPID 0x0014
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#define PCI_VENDORID(x) ((x) & 0xFFFF)
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#define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
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#endif /* !defined(_DC21040_H) */
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