966272ca33
Differential Revision: https://reviews.freebsd.org/D2712 Reviewed by: kib Sponsored by: EMC / Isilon Storage Division
248 lines
8.6 KiB
C
248 lines
8.6 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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* Copyright (c) 1994 John S. Dyson
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91
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* from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30
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* $FreeBSD$
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*/
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#ifndef _MACHINE_VMPARAM_H_
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#define _MACHINE_VMPARAM_H_
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/*
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* Virtual memory related constants, all in bytes
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*/
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#ifndef MAXTSIZ
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#define MAXTSIZ (1*1024*1024*1024) /* max text size */
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#endif
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#ifndef DFLDSIZ
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#define DFLDSIZ (128*1024*1024) /* initial data size limit */
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#endif
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#ifndef MAXDSIZ
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#define MAXDSIZ (1*1024*1024*1024) /* max data size */
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#endif
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#ifndef DFLSSIZ
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#define DFLSSIZ (128*1024*1024) /* initial stack size limit */
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#endif
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#ifndef MAXSSIZ
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#define MAXSSIZ (1*1024*1024*1024) /* max stack size */
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#endif
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#ifndef SGROWSIZ
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#define SGROWSIZ (128*1024) /* amount to grow stack */
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#endif
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/*
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* The physical address space is sparsely populated.
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*/
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#define VM_PHYSSEG_SPARSE
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/*
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* The number of PHYSSEG entries must be one greater than the number
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* of phys_avail entries because the phys_avail entry that spans the
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* largest physical address that is accessible by ISA DMA is split
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* into two PHYSSEG entries.
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*/
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#define VM_PHYSSEG_MAX 64
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/*
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* Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool
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* from which physical pages are allocated and VM_FREEPOOL_DIRECT is
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* the pool from which physical pages for small UMA objects are
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* allocated.
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*/
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#define VM_NFREEPOOL 2
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#define VM_FREEPOOL_DEFAULT 0
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#define VM_FREEPOOL_DIRECT 1
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/*
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* Create two free page lists: VM_FREELIST_DEFAULT is for physical
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* pages that are above the largest physical address that is
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* accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages
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* that are below that address.
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*/
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#define VM_NFREELIST 2
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#define VM_FREELIST_DEFAULT 0
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#define VM_FREELIST_ISADMA 1
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/*
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* An allocation size of 16MB is supported in order to optimize the
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* use of the direct map by UMA. Specifically, a cache line contains
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* at most four TTEs, collectively mapping 16MB of physical memory.
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* By reducing the number of distinct 16MB "pages" that are used by UMA,
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* the physical memory allocator reduces the likelihood of both 4MB
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* page TLB misses and cache misses caused by 4MB page TLB misses.
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*/
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#define VM_NFREEORDER 12
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/*
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* Enable superpage reservations: 1 level.
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*/
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#ifndef VM_NRESERVLEVEL
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#define VM_NRESERVLEVEL 1
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#endif
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/*
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* Level 0 reservations consist of 512 pages.
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*/
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#ifndef VM_LEVEL_0_ORDER
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#define VM_LEVEL_0_ORDER 9
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#endif
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/**
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* Address space layout.
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*
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* UltraSPARC I and II implement a 44 bit virtual address space. The address
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* space is split into 2 regions at each end of the 64 bit address space, with
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* an out of range "hole" in the middle. UltraSPARC III implements the full
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* 64 bit virtual address space, but we don't really have any use for it and
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* 43 bits of user address space is considered to be "enough", so we ignore it.
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*
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* Upper region: 0xffffffffffffffff
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* 0xfffff80000000000
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*
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* Hole: 0xfffff7ffffffffff
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* 0x0000080000000000
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*
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* Lower region: 0x000007ffffffffff
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* 0x0000000000000000
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*
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* In general we ignore the upper region, and use the lower region as mappable
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* space.
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*
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* We define some interesting address constants:
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*
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* VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire
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* 64 bit address space, mostly just for convenience.
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*
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* VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end
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* of the direct mapped region. This maps virtual addresses to physical
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* addresses directly using 4mb tlb entries, with the physical address encoded
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* in the lower 43 bits of virtual address. These mappings are convenient
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* because they do not require page tables, and because they never change they
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* do not require tlb flushes. However, since these mappings are cacheable,
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* we must ensure that all pages accessed this way are either not double
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* mapped, or that all other mappings have virtual color equal to physical
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* color, in order to avoid creating illegal aliases in the data cache.
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*
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* VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of
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* mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically
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* arbitrary, a convenient address is chosen which allows both the kernel text
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* and data and the prom's address space to be mapped with 1 4mb tsb page.
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* VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the
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* amount of physical memory available. Each 4mb tsb page provides 1g of
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* virtual address space, with the only practical limit being available
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* phsyical memory.
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*
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* VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the
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* prom address space. On startup the prom's mappings are duplicated in the
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* kernel tsb, to allow prom memory to be accessed normally by the kernel.
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*
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* VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the
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* user address space. There are some hardware errata about using addresses
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* at the boundary of the va hole, so we allow just under 43 bits of user
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* address space. Note that the kernel and user address spaces overlap, but
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* this doesn't matter because they use different tlb contexts, and because
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* the kernel address space is not mapped into each process' address space.
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*/
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#define VM_MIN_ADDRESS (0x0000000000000000UL)
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#define VM_MAX_ADDRESS (0xffffffffffffffffUL)
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#define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL)
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#define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS)
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#define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL)
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#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address)
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#define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL)
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#define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL)
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#define VM_MIN_USER_ADDRESS (0x0000000000000000UL)
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#define VM_MAX_USER_ADDRESS (0x000007fe00000000UL)
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#define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS)
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#define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS)
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#define KERNBASE (VM_MIN_KERNEL_ADDRESS)
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#define PROMBASE (VM_MIN_PROM_ADDRESS)
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#define USRSTACK (VM_MAX_USER_ADDRESS)
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/*
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* How many physical pages per kmem arena virtual page.
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*/
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#ifndef VM_KMEM_SIZE_SCALE
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#define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2)
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#endif
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/*
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* Optional floor (in bytes) on the size of the kmem arena.
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*/
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#ifndef VM_KMEM_SIZE_MIN
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#define VM_KMEM_SIZE_MIN (16 * 1024 * 1024)
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#endif
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/*
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* Optional ceiling (in bytes) on the size of the kmem arena: 60% of the
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* kernel map.
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*/
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#ifndef VM_KMEM_SIZE_MAX
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#define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \
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VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5)
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#endif
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/*
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* Initial pagein size of beginning of executable file.
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*/
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#ifndef VM_INITIAL_PAGEIN
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#define VM_INITIAL_PAGEIN 16
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#endif
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#define UMA_MD_SMALL_ALLOC
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extern u_int tsb_kernel_ldd_phys;
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extern vm_offset_t vm_max_kernel_address;
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/*
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* Older sparc64 machines have a virtually indexed L1 data cache of 16KB.
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* Consequently, mapping the same physical page multiple times may have
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* caching disabled.
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*/
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#define ZERO_REGION_SIZE PAGE_SIZE
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#define SFBUF
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#define SFBUF_MAP
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#define SFBUF_OPTIONAL_DIRECT_MAP dcache_color_ignore
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#include <machine/tlb.h>
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#define SFBUF_PHYS_DMAP(x) TLB_PHYS_TO_DIRECT(x)
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#endif /* !_MACHINE_VMPARAM_H_ */
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