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DM9100/DM9102 chips. Do not set DC_TX_ONE. The DC_TX_USE_TX_INTR flag causes dc_encap() to set the 'interrupt on TX completion' bit only once every 64 packets. This is an attempt to reduce the number of interrupts generated by the chip. You're supposed to get a 'no more TX buffers left' interrupt once you hit the last packet whether you ask for one or not, however it seems the Davicom chip doesn't generate this interrupt, or at least it doesn't generate it under the same circumstances. The result is that if you transmit n packets, where n is less than 64, and then wait 5 seconds, you'll get a watchdog timeout whether you want one or not. The DC_TX_INTR_ALWAYS causes dc_encap() to request an interrupt for every frame. I'm still waiting on confirmation from a couple of users to see if this fixes their problems with the Davicom DM9102 before I merge this into -stable, but this fixed the problem for me in my own testing so I'm willing to make the change to -current right away.
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