1edbd9d1a6
Refresh upstream driver before impending conversion to iflib.
Major new features:
- Support for Fortville-based 25G adapters
- Support for I2C reads/writes
(To prevent getting or sending corrupt data, you should set
dev.ixl.0.debug.disable_fw_link_management=1 when using I2C
[this will disable link!], then set it to 0 when done. The driver implements
the SIOCGI2C ioctl, so ifconfig -v works for reading I2C data,
but there are read_i2c and write_i2c sysctls under the .debug sysctl tree
[the latter being useful for upper page support in QSFP+]).
- Addition of an iWARP client interface (so the future iWARP driver for
X722 devices can communicate with the base driver).
- Compiling this option in is enabled by default, with "options IXL_IW" in
GENERIC.
Differential Revision: https://reviews.freebsd.org/D9227
Reviewed by: sbruno
MFC after: 2 weeks
Sponsored by: Intel Corporation
606 lines
14 KiB
C
606 lines
14 KiB
C
/******************************************************************************
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Copyright (c) 2013-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixl_pf.h"
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#define IXL_I2C_T_RISE 1
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#define IXL_I2C_T_FALL 1
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#define IXL_I2C_T_SU_DATA 1
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#define IXL_I2C_T_SU_STA 5
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#define IXL_I2C_T_SU_STO 4
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#define IXL_I2C_T_HD_STA 4
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#define IXL_I2C_T_LOW 5
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#define IXL_I2C_T_HIGH 4
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#define IXL_I2C_T_BUF 5
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#define IXL_I2C_CLOCK_STRETCHING_TIMEOUT 500
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#define IXL_I2C_REG(_hw) \
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I40E_GLGEN_I2CPARAMS(((struct i40e_osdep *)(_hw)->back)->i2c_intfc_num)
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static s32 ixl_set_i2c_data(struct ixl_pf *pf, u32 *i2cctl, bool data);
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static bool ixl_get_i2c_data(struct ixl_pf *pf, u32 *i2cctl);
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static void ixl_raise_i2c_clk(struct ixl_pf *pf, u32 *i2cctl);
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static void ixl_lower_i2c_clk(struct ixl_pf *pf, u32 *i2cctl);
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static s32 ixl_clock_out_i2c_bit(struct ixl_pf *pf, bool data);
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static s32 ixl_get_i2c_ack(struct ixl_pf *pf);
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static s32 ixl_clock_out_i2c_byte(struct ixl_pf *pf, u8 data);
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static s32 ixl_clock_in_i2c_bit(struct ixl_pf *pf, bool *data);
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static s32 ixl_clock_in_i2c_byte(struct ixl_pf *pf, u8 *data);
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static void ixl_i2c_bus_clear(struct ixl_pf *pf);
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static void ixl_i2c_start(struct ixl_pf *pf);
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static void ixl_i2c_stop(struct ixl_pf *pf);
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/**
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* ixl_i2c_bus_clear - Clears the I2C bus
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* @hw: pointer to hardware structure
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*
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* Clears the I2C bus by sending nine clock pulses.
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* Used when data line is stuck low.
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**/
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static void
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ixl_i2c_bus_clear(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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u32 i;
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DEBUGFUNC("ixl_i2c_bus_clear");
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ixl_i2c_start(pf);
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ixl_set_i2c_data(pf, &i2cctl, 1);
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for (i = 0; i < 9; i++) {
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Min high period of clock is 4us */
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i40e_usec_delay(IXL_I2C_T_HIGH);
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ixl_lower_i2c_clk(pf, &i2cctl);
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/* Min low period of clock is 4.7us*/
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i40e_usec_delay(IXL_I2C_T_LOW);
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}
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ixl_i2c_start(pf);
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/* Put the i2c bus back to default state */
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ixl_i2c_stop(pf);
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}
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/**
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* ixl_i2c_stop - Sets I2C stop condition
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* @hw: pointer to hardware structure
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*
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* Sets I2C stop condition (Low -> High on SDA while SCL is High)
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**/
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static void
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ixl_i2c_stop(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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DEBUGFUNC("ixl_i2c_stop");
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/* Stop condition must begin with data low and clock high */
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ixl_set_i2c_data(pf, &i2cctl, 0);
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Setup time for stop condition (4us) */
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i40e_usec_delay(IXL_I2C_T_SU_STO);
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ixl_set_i2c_data(pf, &i2cctl, 1);
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/* bus free time between stop and start (4.7us)*/
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i40e_usec_delay(IXL_I2C_T_BUF);
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}
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/**
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* ixl_clock_in_i2c_byte - Clocks in one byte via I2C
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* @hw: pointer to hardware structure
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* @data: data byte to clock in
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*
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* Clocks in one byte data via I2C data/clock
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**/
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static s32
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ixl_clock_in_i2c_byte(struct ixl_pf *pf, u8 *data)
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{
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s32 i;
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bool bit = 0;
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DEBUGFUNC("ixl_clock_in_i2c_byte");
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for (i = 7; i >= 0; i--) {
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ixl_clock_in_i2c_bit(pf, &bit);
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*data |= bit << i;
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}
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return I40E_SUCCESS;
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}
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/**
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* ixl_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
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* @hw: pointer to hardware structure
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* @data: read data value
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*
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* Clocks in one bit via I2C data/clock
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**/
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static s32
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ixl_clock_in_i2c_bit(struct ixl_pf *pf, bool *data)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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DEBUGFUNC("ixl_clock_in_i2c_bit");
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Minimum high period of clock is 4us */
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i40e_usec_delay(IXL_I2C_T_HIGH);
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i2cctl = rd32(hw, IXL_I2C_REG(hw));
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i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK;
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wr32(hw, IXL_I2C_REG(hw), i2cctl);
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ixl_flush(hw);
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i2cctl = rd32(hw, IXL_I2C_REG(hw));
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*data = ixl_get_i2c_data(pf, &i2cctl);
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ixl_lower_i2c_clk(pf, &i2cctl);
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/* Minimum low period of clock is 4.7 us */
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i40e_usec_delay(IXL_I2C_T_LOW);
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return I40E_SUCCESS;
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}
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/**
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* ixl_get_i2c_ack - Polls for I2C ACK
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* @hw: pointer to hardware structure
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*
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* Clocks in/out one bit via I2C data/clock
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**/
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static s32
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ixl_get_i2c_ack(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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s32 status = I40E_SUCCESS;
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u32 i = 0;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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u32 timeout = 10;
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bool ack = 1;
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Minimum high period of clock is 4us */
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i40e_usec_delay(IXL_I2C_T_HIGH);
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i2cctl = rd32(hw, IXL_I2C_REG(hw));
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i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK;
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wr32(hw, IXL_I2C_REG(hw), i2cctl);
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ixl_flush(hw);
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/* Poll for ACK. Note that ACK in I2C spec is
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* transition from 1 to 0 */
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for (i = 0; i < timeout; i++) {
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i2cctl = rd32(hw, IXL_I2C_REG(hw));
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ack = ixl_get_i2c_data(pf, &i2cctl);
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i40e_usec_delay(1);
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if (!ack)
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break;
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}
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if (ack) {
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ixl_dbg(pf, IXL_DBG_I2C, "I2C ack was not received.\n");
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status = I40E_ERR_PHY;
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}
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ixl_lower_i2c_clk(pf, &i2cctl);
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/* Minimum low period of clock is 4.7 us */
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i40e_usec_delay(IXL_I2C_T_LOW);
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return status;
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}
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/**
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* ixl_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
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* @hw: pointer to hardware structure
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* @data: data value to write
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*
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* Clocks out one bit via I2C data/clock
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**/
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static s32
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ixl_clock_out_i2c_bit(struct ixl_pf *pf, bool data)
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{
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struct i40e_hw *hw = &pf->hw;
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s32 status;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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status = ixl_set_i2c_data(pf, &i2cctl, data);
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if (status == I40E_SUCCESS) {
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Minimum high period of clock is 4us */
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i40e_usec_delay(IXL_I2C_T_HIGH);
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ixl_lower_i2c_clk(pf, &i2cctl);
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/* Minimum low period of clock is 4.7 us.
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* This also takes care of the data hold time.
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*/
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i40e_usec_delay(IXL_I2C_T_LOW);
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} else {
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status = I40E_ERR_PHY;
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ixl_dbg(pf, IXL_DBG_I2C, "I2C data was not set to %#x\n", data);
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}
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return status;
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}
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/**
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* ixl_clock_out_i2c_byte - Clocks out one byte via I2C
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* @hw: pointer to hardware structure
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* @data: data byte clocked out
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*
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* Clocks out one byte data via I2C data/clock
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**/
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static s32
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ixl_clock_out_i2c_byte(struct ixl_pf *pf, u8 data)
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{
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struct i40e_hw *hw = &pf->hw;
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s32 status = I40E_SUCCESS;
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s32 i;
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u32 i2cctl;
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bool bit;
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DEBUGFUNC("ixl_clock_out_i2c_byte");
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for (i = 7; i >= 0; i--) {
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bit = (data >> i) & 0x1;
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status = ixl_clock_out_i2c_bit(pf, bit);
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if (status != I40E_SUCCESS)
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break;
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}
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/* Release SDA line (set high) */
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i2cctl = rd32(hw, IXL_I2C_REG(hw));
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i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK;
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i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK);
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wr32(hw, IXL_I2C_REG(hw), i2cctl);
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ixl_flush(hw);
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return status;
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}
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/**
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* ixl_lower_i2c_clk - Lowers the I2C SCL clock
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* @hw: pointer to hardware structure
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* @i2cctl: Current value of I2CCTL register
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*
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* Lowers the I2C clock line '1'->'0'
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**/
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static void
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ixl_lower_i2c_clk(struct ixl_pf *pf, u32 *i2cctl)
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{
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struct i40e_hw *hw = &pf->hw;
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*i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_MASK);
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*i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK);
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wr32(hw, IXL_I2C_REG(hw), *i2cctl);
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ixl_flush(hw);
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/* SCL fall time (300ns) */
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i40e_usec_delay(IXL_I2C_T_FALL);
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}
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/**
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* ixl_raise_i2c_clk - Raises the I2C SCL clock
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* @hw: pointer to hardware structure
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* @i2cctl: Current value of I2CCTL register
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*
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* Raises the I2C clock line '0'->'1'
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**/
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static void
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ixl_raise_i2c_clk(struct ixl_pf *pf, u32 *i2cctl)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 i = 0;
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u32 timeout = IXL_I2C_CLOCK_STRETCHING_TIMEOUT;
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u32 i2cctl_r = 0;
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for (i = 0; i < timeout; i++) {
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*i2cctl |= I40E_GLGEN_I2CPARAMS_CLK_MASK;
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*i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK);
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wr32(hw, IXL_I2C_REG(hw), *i2cctl);
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ixl_flush(hw);
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/* SCL rise time (1000ns) */
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i40e_usec_delay(IXL_I2C_T_RISE);
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i2cctl_r = rd32(hw, IXL_I2C_REG(hw));
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if (i2cctl_r & I40E_GLGEN_I2CPARAMS_CLK_IN_MASK)
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break;
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}
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}
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/**
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* ixl_get_i2c_data - Reads the I2C SDA data bit
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* @hw: pointer to hardware structure
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* @i2cctl: Current value of I2CCTL register
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*
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* Returns the I2C data bit value
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**/
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static bool
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ixl_get_i2c_data(struct ixl_pf *pf, u32 *i2cctl)
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{
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bool data;
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if (*i2cctl & I40E_GLGEN_I2CPARAMS_DATA_IN_MASK)
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data = 1;
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else
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data = 0;
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return data;
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}
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/**
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* ixl_set_i2c_data - Sets the I2C data bit
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* @hw: pointer to hardware structure
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* @i2cctl: Current value of I2CCTL register
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* @data: I2C data value (0 or 1) to set
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*
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* Sets the I2C data bit
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**/
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static s32
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ixl_set_i2c_data(struct ixl_pf *pf, u32 *i2cctl, bool data)
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{
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struct i40e_hw *hw = &pf->hw;
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s32 status = I40E_SUCCESS;
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DEBUGFUNC("ixl_set_i2c_data");
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if (data)
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*i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK;
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else
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*i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK);
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*i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK);
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wr32(hw, IXL_I2C_REG(hw), *i2cctl);
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ixl_flush(hw);
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/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
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i40e_usec_delay(IXL_I2C_T_RISE + IXL_I2C_T_FALL + IXL_I2C_T_SU_DATA);
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/* Verify data was set correctly */
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*i2cctl = rd32(hw, IXL_I2C_REG(hw));
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if (data != ixl_get_i2c_data(pf, i2cctl)) {
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status = I40E_ERR_PHY;
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ixl_dbg(pf, IXL_DBG_I2C, "Error - I2C data was not set to %X.\n", data);
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}
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return status;
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}
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/**
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* ixl_i2c_start - Sets I2C start condition
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* Sets I2C start condition (High -> Low on SDA while SCL is High)
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**/
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static void
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ixl_i2c_start(struct ixl_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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DEBUGFUNC("ixl_i2c_start");
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/* Start condition must begin with data and clock high */
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ixl_set_i2c_data(pf, &i2cctl, 1);
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ixl_raise_i2c_clk(pf, &i2cctl);
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/* Setup time for start condition (4.7us) */
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i40e_usec_delay(IXL_I2C_T_SU_STA);
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ixl_set_i2c_data(pf, &i2cctl, 0);
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/* Hold time for start condition (4us) */
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i40e_usec_delay(IXL_I2C_T_HD_STA);
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ixl_lower_i2c_clk(pf, &i2cctl);
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/* Minimum low period of clock is 4.7 us */
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i40e_usec_delay(IXL_I2C_T_LOW);
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}
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/**
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* ixl_read_i2c_byte - Reads 8 bit word over I2C
|
|
**/
|
|
s32
|
|
ixl_read_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
|
|
u8 dev_addr, u8 *data)
|
|
{
|
|
struct i40e_hw *hw = &pf->hw;
|
|
u32 max_retry = 10;
|
|
u32 retry = 0;
|
|
bool nack = 1;
|
|
s32 status;
|
|
*data = 0;
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|
|
|
u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
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|
i2cctl |= I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
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|
wr32(hw, IXL_I2C_REG(hw), i2cctl);
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|
ixl_flush(hw);
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|
|
|
do {
|
|
ixl_i2c_start(pf);
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|
|
|
/* Device Address and write indication */
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|
status = ixl_clock_out_i2c_byte(pf, dev_addr);
|
|
if (status != I40E_SUCCESS) {
|
|
ixl_dbg(pf, IXL_DBG_I2C, "dev_addr clock out error\n");
|
|
goto fail;
|
|
}
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS) {
|
|
ixl_dbg(pf, IXL_DBG_I2C, "dev_addr i2c ack error\n");
|
|
goto fail;
|
|
}
|
|
|
|
status = ixl_clock_out_i2c_byte(pf, byte_offset);
|
|
if (status != I40E_SUCCESS) {
|
|
ixl_dbg(pf, IXL_DBG_I2C, "byte_offset clock out error\n");
|
|
goto fail;
|
|
}
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS) {
|
|
ixl_dbg(pf, IXL_DBG_I2C, "byte_offset i2c ack error\n");
|
|
goto fail;
|
|
}
|
|
|
|
ixl_i2c_start(pf);
|
|
|
|
/* Device Address and read indication */
|
|
status = ixl_clock_out_i2c_byte(pf, (dev_addr | 0x1));
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_clock_in_i2c_byte(pf, data);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_clock_out_i2c_bit(pf, nack);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
ixl_i2c_stop(pf);
|
|
status = I40E_SUCCESS;
|
|
goto done;
|
|
|
|
fail:
|
|
ixl_i2c_bus_clear(pf);
|
|
i40e_msec_delay(100);
|
|
retry++;
|
|
if (retry < max_retry)
|
|
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error - Retrying.\n");
|
|
else
|
|
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error.\n");
|
|
|
|
} while (retry < max_retry);
|
|
done:
|
|
i2cctl = rd32(hw, IXL_I2C_REG(hw));
|
|
i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
|
|
wr32(hw, IXL_I2C_REG(hw), i2cctl);
|
|
ixl_flush(hw);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ixl_write_i2c_byte - Writes 8 bit word over I2C
|
|
**/
|
|
s32
|
|
ixl_write_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
|
|
u8 dev_addr, u8 data)
|
|
{
|
|
struct i40e_hw *hw = &pf->hw;
|
|
s32 status = I40E_SUCCESS;
|
|
u32 max_retry = 1;
|
|
u32 retry = 0;
|
|
|
|
u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
|
|
i2cctl |= I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
|
|
wr32(hw, IXL_I2C_REG(hw), i2cctl);
|
|
ixl_flush(hw);
|
|
|
|
do {
|
|
ixl_i2c_start(pf);
|
|
|
|
status = ixl_clock_out_i2c_byte(pf, dev_addr);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_clock_out_i2c_byte(pf, byte_offset);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_clock_out_i2c_byte(pf, data);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
status = ixl_get_i2c_ack(pf);
|
|
if (status != I40E_SUCCESS)
|
|
goto fail;
|
|
|
|
ixl_i2c_stop(pf);
|
|
goto write_byte_out;
|
|
|
|
fail:
|
|
ixl_i2c_bus_clear(pf);
|
|
i40e_msec_delay(100);
|
|
retry++;
|
|
if (retry < max_retry)
|
|
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write error - Retrying.\n");
|
|
else
|
|
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write error.\n");
|
|
} while (retry < max_retry);
|
|
|
|
write_byte_out:
|
|
i2cctl = rd32(hw, IXL_I2C_REG(hw));
|
|
i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
|
|
wr32(hw, IXL_I2C_REG(hw), i2cctl);
|
|
ixl_flush(hw);
|
|
|
|
return status;
|
|
}
|
|
|