cdaba8920e
Submitted by: "Duvvuru,Venkat Kumar" <VenkatKumar.Duvvuru Emulex.Com> MFC after: 3 days
588 lines
14 KiB
C
588 lines
14 KiB
C
/*-
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* Copyright (C) 2012 Emulex
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Emulex Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contact Information:
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* freebsd-drivers@emulex.com
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*
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* Emulex
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* 3333 Susan Street
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* Costa Mesa, CA 92626
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*/
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/* $FreeBSD$ */
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#include "oce_if.h"
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static int oce_POST(POCE_SOFTC sc);
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/**
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* @brief Function to post status
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* @param sc software handle to the device
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*/
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static int
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oce_POST(POCE_SOFTC sc)
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{
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mpu_ep_semaphore_t post_status;
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int tmo = 60000;
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/* read semaphore CSR */
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post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
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/* if host is ready then wait for fw ready else send POST */
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if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
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post_status.bits.stage = POST_STAGE_CHIP_RESET;
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OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
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}
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/* wait for FW ready */
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for (;;) {
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if (--tmo == 0)
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break;
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DELAY(1000);
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post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
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if (post_status.bits.error) {
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device_printf(sc->dev,
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"POST failed: %x\n", post_status.dw0);
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return ENXIO;
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}
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if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
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return 0;
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}
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device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);
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return ENXIO;
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}
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/**
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* @brief Function for hardware initialization
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* @param sc software handle to the device
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*/
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int
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oce_hw_init(POCE_SOFTC sc)
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{
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int rc = 0;
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rc = oce_POST(sc);
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if (rc)
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return rc;
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/* create the bootstrap mailbox */
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rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
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if (rc) {
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device_printf(sc->dev, "Mailbox alloc failed\n");
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return rc;
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}
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rc = oce_reset_fun(sc);
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if (rc)
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goto error;
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rc = oce_mbox_init(sc);
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if (rc)
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goto error;
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rc = oce_get_fw_version(sc);
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if (rc)
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goto error;
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rc = oce_get_fw_config(sc);
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if (rc)
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goto error;
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sc->macaddr.size_of_struct = 6;
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rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
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&sc->macaddr);
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if (rc)
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goto error;
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
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rc = oce_mbox_check_native_mode(sc);
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if (rc)
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goto error;
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} else
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sc->be3_native = 0;
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return rc;
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error:
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oce_dma_free(sc, &sc->bsmbx);
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device_printf(sc->dev, "Hardware initialisation failed\n");
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return rc;
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}
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/**
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* @brief Releases the obtained pci resources
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* @param sc software handle to the device
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*/
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void
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oce_hw_pci_free(POCE_SOFTC sc)
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{
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int pci_cfg_barnum = 0;
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
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pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
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else
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pci_cfg_barnum = OCE_DEV_CFG_BAR;
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if (sc->devcfg_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);
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sc->devcfg_res = (struct resource *)NULL;
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sc->devcfg_btag = (bus_space_tag_t) 0;
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sc->devcfg_bhandle = (bus_space_handle_t)0;
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sc->devcfg_vhandle = (void *)NULL;
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}
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if (sc->csr_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);
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sc->csr_res = (struct resource *)NULL;
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sc->csr_btag = (bus_space_tag_t)0;
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sc->csr_bhandle = (bus_space_handle_t)0;
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sc->csr_vhandle = (void *)NULL;
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}
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if (sc->db_res != NULL) {
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bus_release_resource(sc->dev,
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SYS_RES_MEMORY,
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PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);
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sc->db_res = (struct resource *)NULL;
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sc->db_btag = (bus_space_tag_t)0;
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sc->db_bhandle = (bus_space_handle_t)0;
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sc->db_vhandle = (void *)NULL;
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}
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}
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/**
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* @brief Function to get the PCI capabilities
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* @param sc software handle to the device
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*/
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static
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void oce_get_pci_capabilities(POCE_SOFTC sc)
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{
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uint32_t val;
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if (pci_find_cap(sc->dev, PCIY_PCIX, &val) == 0) {
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if (val != 0)
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sc->flags |= OCE_FLAGS_PCIX;
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}
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if (pci_find_cap(sc->dev, PCIY_EXPRESS, &val) == 0) {
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if (val != 0) {
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uint16_t link_status =
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pci_read_config(sc->dev, val + 0x12, 2);
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sc->flags |= OCE_FLAGS_PCIE;
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sc->pcie_link_speed = link_status & 0xf;
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sc->pcie_link_width = (link_status >> 4) & 0x3f;
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}
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}
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if (pci_find_cap(sc->dev, PCIY_MSI, &val) == 0) {
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if (val != 0)
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sc->flags |= OCE_FLAGS_MSI_CAPABLE;
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}
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if (pci_find_cap(sc->dev, PCIY_MSIX, &val) == 0) {
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if (val != 0) {
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val = pci_msix_count(sc->dev);
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sc->flags |= OCE_FLAGS_MSIX_CAPABLE;
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}
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}
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}
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/**
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* @brief Allocate PCI resources.
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*
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* @param sc software handle to the device
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* @returns 0 if successful, or error
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*/
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int
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oce_hw_pci_alloc(POCE_SOFTC sc)
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{
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int rr, pci_cfg_barnum = 0;
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pci_sli_intf_t intf;
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pci_enable_busmaster(sc->dev);
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oce_get_pci_capabilities(sc);
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sc->fn = pci_get_function(sc->dev);
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/* setup the device config region */
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if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
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pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
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else
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pci_cfg_barnum = OCE_DEV_CFG_BAR;
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rr = PCIR_BAR(pci_cfg_barnum);
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if (IS_BE(sc))
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sc->devcfg_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr,
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RF_ACTIVE|RF_SHAREABLE);
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else
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sc->devcfg_res = bus_alloc_resource(sc->dev,
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SYS_RES_MEMORY, &rr,
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0ul, ~0ul, 32768,
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RF_ACTIVE|RF_SHAREABLE);
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if (!sc->devcfg_res)
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goto error;
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sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);
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sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);
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sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);
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/* Read the SLI_INTF register and determine whether we
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* can use this port and its features
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*/
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intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);
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if (intf.bits.sli_valid != OCE_INTF_VALID_SIG)
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goto error;
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if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) {
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device_printf(sc->dev, "Adapter doesnt support SLI4\n");
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goto error;
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}
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if (intf.bits.sli_if_type == OCE_INTF_IF_TYPE_1)
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sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;
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if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
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sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
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if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
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sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
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/* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
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if (IS_BE(sc)) {
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/* set up CSR region */
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rr = PCIR_BAR(OCE_PCI_CSR_BAR);
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sc->csr_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
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if (!sc->csr_res)
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goto error;
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sc->csr_btag = rman_get_bustag(sc->csr_res);
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sc->csr_bhandle = rman_get_bushandle(sc->csr_res);
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sc->csr_vhandle = rman_get_virtual(sc->csr_res);
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/* set up DB doorbell region */
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rr = PCIR_BAR(OCE_PCI_DB_BAR);
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sc->db_res = bus_alloc_resource_any(sc->dev,
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SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
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if (!sc->db_res)
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goto error;
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sc->db_btag = rman_get_bustag(sc->db_res);
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sc->db_bhandle = rman_get_bushandle(sc->db_res);
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sc->db_vhandle = rman_get_virtual(sc->db_res);
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}
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return 0;
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error:
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oce_hw_pci_free(sc);
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return ENXIO;
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}
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/**
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* @brief Function for device shutdown
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* @param sc software handle to the device
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* @returns 0 on success, error otherwise
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*/
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void
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oce_hw_shutdown(POCE_SOFTC sc)
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{
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oce_stats_free(sc);
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/* disable hardware interrupts */
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oce_hw_intr_disable(sc);
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#if defined(INET6) || defined(INET)
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/* Free LRO resources */
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oce_free_lro(sc);
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#endif
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/* Release queue*/
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oce_queue_release_all(sc);
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/*Delete Network Interface*/
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oce_delete_nw_interface(sc);
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/* After fw clean we dont send any cmds to fw.*/
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oce_fw_clean(sc);
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/* release intr resources */
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oce_intr_free(sc);
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/* release PCI resources */
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oce_hw_pci_free(sc);
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/* free mbox specific resources */
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LOCK_DESTROY(&sc->bmbx_lock);
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LOCK_DESTROY(&sc->dev_lock);
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oce_dma_free(sc, &sc->bsmbx);
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}
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/**
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* @brief Function for creating nw interface.
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* @param sc software handle to the device
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* @returns 0 on success, error otherwise
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*/
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int
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oce_create_nw_interface(POCE_SOFTC sc)
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{
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int rc;
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uint32_t capab_flags;
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uint32_t capab_en_flags;
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/* interface capabilities to give device when creating interface */
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capab_flags = OCE_CAPAB_FLAGS;
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/* capabilities to enable by default (others set dynamically) */
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capab_en_flags = OCE_CAPAB_ENABLE;
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if (IS_XE201(sc)) {
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/* LANCER A0 workaround */
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capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
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capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
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}
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/* enable capabilities controlled via driver startup parameters */
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if (sc->rss_enable)
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capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
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else {
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capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
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capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
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}
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rc = oce_if_create(sc,
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capab_flags,
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capab_en_flags,
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0, &sc->macaddr.mac_addr[0], &sc->if_id);
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if (rc)
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return rc;
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atomic_inc_32(&sc->nifs);
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sc->if_cap_flags = capab_en_flags;
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/* set default flow control */
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rc = oce_set_flow_control(sc, sc->flow_control);
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if (rc)
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goto error;
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rc = oce_rxf_set_promiscuous(sc, sc->promisc);
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if (rc)
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goto error;
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return rc;
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error:
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oce_delete_nw_interface(sc);
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return rc;
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}
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/**
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* @brief Function to delete a nw interface.
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* @param sc software handle to the device
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*/
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void
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oce_delete_nw_interface(POCE_SOFTC sc)
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{
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/* currently only single interface is implmeneted */
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if (sc->nifs > 0) {
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oce_if_del(sc, sc->if_id);
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atomic_dec_32(&sc->nifs);
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}
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}
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/**
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* @brief Soft reset.
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* @param sc software handle to the device
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* @returns 0 on success, error otherwise
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*/
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int
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oce_pci_soft_reset(POCE_SOFTC sc)
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{
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int rc;
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mpu_ep_control_t ctrl;
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ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
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ctrl.bits.cpu_reset = 1;
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OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
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DELAY(50);
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rc=oce_POST(sc);
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return rc;
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}
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/**
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* @brief Function for hardware start
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* @param sc software handle to the device
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* @returns 0 on success, error otherwise
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*/
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int
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oce_hw_start(POCE_SOFTC sc)
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{
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struct link_status link = { 0 };
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int rc = 0;
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rc = oce_get_link_status(sc, &link);
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if (rc)
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return 1;
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if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) {
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sc->link_status = NTWK_LOGICAL_LINK_UP;
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if_link_state_change(sc->ifp, LINK_STATE_UP);
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} else {
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sc->link_status = NTWK_LOGICAL_LINK_DOWN;
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if_link_state_change(sc->ifp, LINK_STATE_DOWN);
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}
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if (link.mac_speed > 0 && link.mac_speed < 5)
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sc->link_speed = link.mac_speed;
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else
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sc->link_speed = 0;
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sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;
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rc = oce_start_mq(sc->mq);
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/* we need to get MCC aync events. So enable intrs and arm
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first EQ, Other EQs will be armed after interface is UP
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*/
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oce_hw_intr_enable(sc);
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oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
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/* Send first mcc cmd and after that we get gracious
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MCC notifications from FW
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*/
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oce_first_mcc_cmd(sc);
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return rc;
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}
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/**
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* @brief Function for hardware enable interupts.
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* @param sc software handle to the device
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*/
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void
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oce_hw_intr_enable(POCE_SOFTC sc)
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{
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uint32_t reg;
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reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
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reg |= HOSTINTR_MASK;
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OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
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}
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|
|
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/**
|
|
* @brief Function for hardware disable interupts
|
|
* @param sc software handle to the device
|
|
*/
|
|
void
|
|
oce_hw_intr_disable(POCE_SOFTC sc)
|
|
{
|
|
uint32_t reg;
|
|
|
|
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
|
|
reg &= ~HOSTINTR_MASK;
|
|
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
* @brief Function for hardware update multicast filter
|
|
* @param sc software handle to the device
|
|
*/
|
|
int
|
|
oce_hw_update_multicast(POCE_SOFTC sc)
|
|
{
|
|
struct ifnet *ifp = sc->ifp;
|
|
struct ifmultiaddr *ifma;
|
|
struct mbx_set_common_iface_multicast *req = NULL;
|
|
OCE_DMA_MEM dma;
|
|
int rc = 0;
|
|
|
|
/* Allocate DMA mem*/
|
|
if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),
|
|
&dma, 0))
|
|
return ENOMEM;
|
|
|
|
req = OCE_DMAPTR(&dma, struct mbx_set_common_iface_multicast);
|
|
bzero(req, sizeof(struct mbx_set_common_iface_multicast));
|
|
|
|
#if __FreeBSD_version > 800000
|
|
if_maddr_rlock(ifp);
|
|
#endif
|
|
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
|
if (ifma->ifma_addr->sa_family != AF_LINK)
|
|
continue;
|
|
|
|
if (req->params.req.num_mac == OCE_MAX_MC_FILTER_SIZE) {
|
|
/*More multicast addresses than our hardware table
|
|
So Enable multicast promiscus in our hardware to
|
|
accept all multicat packets
|
|
*/
|
|
req->params.req.promiscuous = 1;
|
|
break;
|
|
}
|
|
bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
|
|
&req->params.req.mac[req->params.req.num_mac],
|
|
ETH_ADDR_LEN);
|
|
req->params.req.num_mac = req->params.req.num_mac + 1;
|
|
}
|
|
#if __FreeBSD_version > 800000
|
|
if_maddr_runlock(ifp);
|
|
#endif
|
|
req->params.req.if_id = sc->if_id;
|
|
rc = oce_update_multicast(sc, &dma);
|
|
oce_dma_free(sc, &dma);
|
|
return rc;
|
|
}
|
|
|