76a869385c
It's not currently used; it didn't build on 32-bit and the previous build fix is incorrect. If we really implement self-tests we can do this again properly. Submitted by: Ben Hutchings <bwh -at- solarflare.com> MFC after: 3 weeks
557 lines
12 KiB
C
557 lines
12 KiB
C
/*-
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* Copyright (c) 2010-2011 Solarflare Communications, Inc.
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* All rights reserved.
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*
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* This software was developed in part by Philip Paeps under contract for
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* Solarflare Communications, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <sys/syslog.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "common/efx.h"
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#include "sfxge.h"
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static int
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sfxge_intr_line_filter(void *arg)
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{
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struct sfxge_evq *evq;
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struct sfxge_softc *sc;
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efx_nic_t *enp;
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struct sfxge_intr *intr;
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boolean_t fatal;
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uint32_t qmask;
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evq = (struct sfxge_evq *)arg;
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sc = evq->sc;
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enp = sc->enp;
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intr = &sc->intr;
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KASSERT(intr != NULL, ("intr == NULL"));
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KASSERT(intr->type == EFX_INTR_LINE,
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("intr->type != EFX_INTR_LINE"));
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if (intr->state != SFXGE_INTR_STARTED)
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return FILTER_STRAY;
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(void)efx_intr_status_line(enp, &fatal, &qmask);
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if (fatal) {
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(void) efx_intr_disable(enp);
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(void) efx_intr_fatal(enp);
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return FILTER_HANDLED;
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}
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if (qmask != 0) {
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intr->zero_count = 0;
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return FILTER_SCHEDULE_THREAD;
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}
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/* SF bug 15783: If the function is not asserting its IRQ and
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* we read the queue mask on the cycle before a flag is added
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* to the mask, this inhibits the function from asserting the
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* IRQ even though we don't see the flag set. To work around
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* this, we must re-prime all event queues and report the IRQ
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* as handled when we see a mask of zero. To allow for shared
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* IRQs, we don't repeat this if we see a mask of zero twice
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* or more in a row.
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*/
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if (intr->zero_count++ == 0) {
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if (evq->init_state == SFXGE_EVQ_STARTED) {
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if (efx_ev_qpending(evq->common, evq->read_ptr))
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return FILTER_SCHEDULE_THREAD;
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efx_ev_qprime(evq->common, evq->read_ptr);
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return FILTER_HANDLED;
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}
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}
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return FILTER_STRAY;
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}
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static void
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sfxge_intr_line(void *arg)
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{
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struct sfxge_evq *evq = arg;
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struct sfxge_softc *sc = evq->sc;
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(void)sfxge_ev_qpoll(sc, 0);
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}
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static void
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sfxge_intr_message(void *arg)
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{
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struct sfxge_evq *evq;
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struct sfxge_softc *sc;
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efx_nic_t *enp;
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struct sfxge_intr *intr;
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unsigned int index;
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boolean_t fatal;
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evq = (struct sfxge_evq *)arg;
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sc = evq->sc;
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enp = sc->enp;
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intr = &sc->intr;
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index = evq->index;
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KASSERT(intr != NULL, ("intr == NULL"));
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KASSERT(intr->type == EFX_INTR_MESSAGE,
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("intr->type != EFX_INTR_MESSAGE"));
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if (intr->state != SFXGE_INTR_STARTED)
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return;
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(void)efx_intr_status_message(enp, index, &fatal);
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if (fatal) {
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(void)efx_intr_disable(enp);
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(void)efx_intr_fatal(enp);
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return;
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}
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(void)sfxge_ev_qpoll(sc, index);
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}
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static int
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sfxge_intr_bus_enable(struct sfxge_softc *sc)
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{
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struct sfxge_intr *intr;
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struct sfxge_intr_hdl *table;
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driver_filter_t *filter;
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driver_intr_t *handler;
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int index;
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int err;
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intr = &sc->intr;
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table = intr->table;
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switch (intr->type) {
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case EFX_INTR_MESSAGE:
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filter = NULL; /* not shared */
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handler = sfxge_intr_message;
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break;
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case EFX_INTR_LINE:
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filter = sfxge_intr_line_filter;
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handler = sfxge_intr_line;
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break;
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default:
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KASSERT(0, ("Invalid interrupt type"));
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return EINVAL;
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}
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/* Try to add the handlers */
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for (index = 0; index < intr->n_alloc; index++) {
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if ((err = bus_setup_intr(sc->dev, table[index].eih_res,
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INTR_MPSAFE|INTR_TYPE_NET, filter, handler,
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sc->evq[index], &table[index].eih_tag)) != 0) {
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goto fail;
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}
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#ifdef SFXGE_HAVE_DESCRIBE_INTR
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if (intr->n_alloc > 1)
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bus_describe_intr(sc->dev, table[index].eih_res,
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table[index].eih_tag, "%d", index);
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#endif
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bus_bind_intr(sc->dev, table[index].eih_res, index);
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}
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return (0);
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fail:
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/* Remove remaining handlers */
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while (--index >= 0)
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bus_teardown_intr(sc->dev, table[index].eih_res,
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table[index].eih_tag);
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return (err);
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}
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static void
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sfxge_intr_bus_disable(struct sfxge_softc *sc)
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{
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struct sfxge_intr *intr;
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struct sfxge_intr_hdl *table;
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int i;
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intr = &sc->intr;
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table = intr->table;
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/* Remove all handlers */
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for (i = 0; i < intr->n_alloc; i++)
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bus_teardown_intr(sc->dev, table[i].eih_res,
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table[i].eih_tag);
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}
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static int
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sfxge_intr_alloc(struct sfxge_softc *sc, int count)
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{
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device_t dev;
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struct sfxge_intr_hdl *table;
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struct sfxge_intr *intr;
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struct resource *res;
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int rid;
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int error;
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int i;
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dev = sc->dev;
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intr = &sc->intr;
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error = 0;
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table = malloc(count * sizeof(struct sfxge_intr_hdl),
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M_SFXGE, M_WAITOK);
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intr->table = table;
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for (i = 0; i < count; i++) {
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rid = i + 1;
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res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (res == NULL) {
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device_printf(dev, "Couldn't allocate interrupts for "
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"message %d\n", rid);
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error = ENOMEM;
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break;
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}
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table[i].eih_rid = rid;
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table[i].eih_res = res;
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}
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if (error) {
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count = i - 1;
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for (i = 0; i < count; i++)
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bus_release_resource(dev, SYS_RES_IRQ,
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table[i].eih_rid, table[i].eih_res);
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}
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return (error);
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}
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static void
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sfxge_intr_teardown_msix(struct sfxge_softc *sc)
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{
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device_t dev;
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struct resource *resp;
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int rid;
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dev = sc->dev;
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resp = sc->intr.msix_res;
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rid = rman_get_rid(resp);
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bus_release_resource(dev, SYS_RES_MEMORY, rid, resp);
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}
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static int
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sfxge_intr_setup_msix(struct sfxge_softc *sc)
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{
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struct sfxge_intr *intr;
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struct resource *resp;
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device_t dev;
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int count;
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int rid;
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dev = sc->dev;
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intr = &sc->intr;
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/* Check if MSI-X is available. */
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count = pci_msix_count(dev);
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if (count == 0)
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return (EINVAL);
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/* Limit the number of interrupts to the number of CPUs. */
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if (count > mp_ncpus)
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count = mp_ncpus;
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/* Not very likely these days... */
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if (count > EFX_MAXRSS)
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count = EFX_MAXRSS;
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rid = PCIR_BAR(4);
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resp = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (resp == NULL)
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return (ENOMEM);
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if (pci_alloc_msix(dev, &count) != 0) {
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bus_release_resource(dev, SYS_RES_MEMORY, rid, resp);
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return (ENOMEM);
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}
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/* Allocate interrupt handlers. */
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if (sfxge_intr_alloc(sc, count) != 0) {
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bus_release_resource(dev, SYS_RES_MEMORY, rid, resp);
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pci_release_msi(dev);
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return (ENOMEM);
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}
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intr->type = EFX_INTR_MESSAGE;
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intr->n_alloc = count;
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intr->msix_res = resp;
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return (0);
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}
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static int
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sfxge_intr_setup_msi(struct sfxge_softc *sc)
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{
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struct sfxge_intr_hdl *table;
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struct sfxge_intr *intr;
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device_t dev;
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int count;
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int error;
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dev = sc->dev;
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intr = &sc->intr;
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table = intr->table;
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/*
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* Check if MSI is available. All messages must be written to
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* the same address and on x86 this means the IRQs have the
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* same CPU affinity. So we only ever allocate 1.
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*/
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count = pci_msi_count(dev) ? 1 : 0;
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if (count == 0)
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return (EINVAL);
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if ((error = pci_alloc_msi(dev, &count)) != 0)
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return (ENOMEM);
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/* Allocate interrupt handler. */
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if (sfxge_intr_alloc(sc, count) != 0) {
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pci_release_msi(dev);
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return (ENOMEM);
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}
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intr->type = EFX_INTR_MESSAGE;
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intr->n_alloc = count;
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return (0);
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}
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static int
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sfxge_intr_setup_fixed(struct sfxge_softc *sc)
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{
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struct sfxge_intr_hdl *table;
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struct sfxge_intr *intr;
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struct resource *res;
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device_t dev;
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int rid;
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dev = sc->dev;
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intr = &sc->intr;
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rid = 0;
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res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (res == NULL)
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return (ENOMEM);
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table = malloc(sizeof(struct sfxge_intr_hdl), M_SFXGE, M_WAITOK);
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table[0].eih_rid = rid;
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table[0].eih_res = res;
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intr->type = EFX_INTR_LINE;
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intr->n_alloc = 1;
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intr->table = table;
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return (0);
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}
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static const char *const __sfxge_err[] = {
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"",
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"SRAM out-of-bounds",
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"Buffer ID out-of-bounds",
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"Internal memory parity",
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"Receive buffer ownership",
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"Transmit buffer ownership",
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"Receive descriptor ownership",
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"Transmit descriptor ownership",
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"Event queue ownership",
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"Event queue FIFO overflow",
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"Illegal address",
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"SRAM parity"
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};
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void
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sfxge_err(efsys_identifier_t *arg, unsigned int code, uint32_t dword0,
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uint32_t dword1)
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{
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struct sfxge_softc *sc = (struct sfxge_softc *)arg;
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device_t dev = sc->dev;
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log(LOG_WARNING, "[%s%d] FATAL ERROR: %s (0x%08x%08x)",
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device_get_name(dev), device_get_unit(dev),
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__sfxge_err[code], dword1, dword0);
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}
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void
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sfxge_intr_stop(struct sfxge_softc *sc)
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{
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struct sfxge_intr *intr;
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intr = &sc->intr;
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KASSERT(intr->state == SFXGE_INTR_STARTED,
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("Interrupts not started"));
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intr->state = SFXGE_INTR_INITIALIZED;
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/* Disable interrupts at the NIC */
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efx_intr_disable(sc->enp);
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/* Disable interrupts at the bus */
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sfxge_intr_bus_disable(sc);
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/* Tear down common code interrupt bits. */
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efx_intr_fini(sc->enp);
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}
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int
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sfxge_intr_start(struct sfxge_softc *sc)
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{
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struct sfxge_intr *intr;
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efsys_mem_t *esmp;
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int rc;
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intr = &sc->intr;
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esmp = &intr->status;
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KASSERT(intr->state == SFXGE_INTR_INITIALIZED,
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("Interrupts not initialized"));
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/* Zero the memory. */
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(void)memset(esmp->esm_base, 0, EFX_INTR_SIZE);
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/* Initialize common code interrupt bits. */
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(void)efx_intr_init(sc->enp, intr->type, esmp);
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/* Enable interrupts at the bus */
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if ((rc = sfxge_intr_bus_enable(sc)) != 0)
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goto fail;
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intr->state = SFXGE_INTR_STARTED;
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/* Enable interrupts at the NIC */
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efx_intr_enable(sc->enp);
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return (0);
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fail:
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/* Tear down common code interrupt bits. */
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efx_intr_fini(sc->enp);
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intr->state = SFXGE_INTR_INITIALIZED;
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return (rc);
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}
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void
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sfxge_intr_fini(struct sfxge_softc *sc)
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{
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struct sfxge_intr_hdl *table;
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struct sfxge_intr *intr;
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efsys_mem_t *esmp;
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device_t dev;
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int i;
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dev = sc->dev;
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intr = &sc->intr;
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esmp = &intr->status;
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table = intr->table;
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KASSERT(intr->state == SFXGE_INTR_INITIALIZED,
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("intr->state != SFXGE_INTR_INITIALIZED"));
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/* Free DMA memory. */
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sfxge_dma_free(esmp);
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/* Free interrupt handles. */
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for (i = 0; i < intr->n_alloc; i++)
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bus_release_resource(dev, SYS_RES_IRQ,
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table[i].eih_rid, table[i].eih_res);
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if (table[0].eih_rid != 0)
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pci_release_msi(dev);
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if (intr->msix_res != NULL)
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sfxge_intr_teardown_msix(sc);
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/* Free the handle table */
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free(table, M_SFXGE);
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intr->table = NULL;
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intr->n_alloc = 0;
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/* Clear the interrupt type */
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intr->type = EFX_INTR_INVALID;
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intr->state = SFXGE_INTR_UNINITIALIZED;
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}
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int
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sfxge_intr_init(struct sfxge_softc *sc)
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{
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device_t dev;
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struct sfxge_intr *intr;
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efsys_mem_t *esmp;
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int rc;
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dev = sc->dev;
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intr = &sc->intr;
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esmp = &intr->status;
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KASSERT(intr->state == SFXGE_INTR_UNINITIALIZED,
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("Interrupts already initialized"));
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/* Try to setup MSI-X or MSI interrupts if available. */
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if ((rc = sfxge_intr_setup_msix(sc)) == 0)
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device_printf(dev, "Using MSI-X interrupts\n");
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else if ((rc = sfxge_intr_setup_msi(sc)) == 0)
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device_printf(dev, "Using MSI interrupts\n");
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else if ((rc = sfxge_intr_setup_fixed(sc)) == 0) {
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device_printf(dev, "Using fixed interrupts\n");
|
|
} else {
|
|
device_printf(dev, "Couldn't setup interrupts\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Set up DMA for interrupts. */
|
|
if ((rc = sfxge_dma_alloc(sc, EFX_INTR_SIZE, esmp)) != 0)
|
|
return (ENOMEM);
|
|
|
|
intr->state = SFXGE_INTR_INITIALIZED;
|
|
|
|
return (0);
|
|
}
|