352e51d169
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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* @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _CPUINFO_H_
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#define _CPUINFO_H_
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/*
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* Exported definitions unique to NetBSD/mips cpu support.
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*/
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#ifdef _KERNEL
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#ifndef LOCORE
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struct mips_cpuinfo {
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u_int8_t cpu_vendor;
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u_int8_t cpu_rev;
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u_int8_t cpu_impl;
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u_int8_t tlb_type;
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u_int16_t tlb_nentries;
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u_int8_t icache_virtual;
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struct {
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u_int8_t ic_size;
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u_int8_t ic_linesize;
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u_int8_t ic_nways;
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u_int16_t ic_nsets;
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u_int8_t dc_size;
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u_int8_t dc_linesize;
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u_int8_t dc_nways;
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u_int16_t dc_nsets;
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} l1;
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};
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/* TODO: Merge above structure with NetBSD's below. */
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struct cpu_info {
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#ifdef notyet
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struct schedstate_percpu ci_schedstate; /* scheduler state */
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#endif
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u_long ci_cpu_freq; /* CPU frequency */
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u_long ci_cycles_per_hz; /* CPU freq / hz */
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u_long ci_divisor_delay; /* for delay/DELAY */
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u_long ci_divisor_recip; /* scaled reciprocal of previous;
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see below */
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#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
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u_long ci_spin_locks; /* # of spin locks held */
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u_long ci_simple_locks; /* # of simple locks held */
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#endif
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};
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/*
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* To implement a more accurate microtime using the CP0 COUNT register
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* we need to divide that register by the number of cycles per MHz.
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* But...
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*
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* DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT
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* and MULTU are only 12 clocks on the same CPU.
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*
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* The strategy we use is to calculate the reciprical of cycles per MHz,
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* scaled by 1<<32. Then we can simply issue a MULTU and pluck of the
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* HI register and have the results of the division.
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*/
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#define MIPS_SET_CI_RECIPRICAL(cpu) \
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do { \
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KASSERT((cpu)->ci_divisor_delay != 0, ("divisor delay")); \
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(cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \
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} while (0)
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#define MIPS_COUNT_TO_MHZ(cpu, count, res) \
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__asm __volatile ("multu %1,%2 ; mfhi %0" \
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: "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip))
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extern struct cpu_info cpu_info_store;
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#if 0
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#define curcpu() (&cpu_info_store)
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#define cpu_number() (0)
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#endif
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* _CPUINFO_H_ */
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