232 lines
8.0 KiB
Diff
232 lines
8.0 KiB
Diff
Pull in r198286 from upstream llvm trunk (by Venkatraman Govindaraju):
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[Sparc] Handle atomic loads/stores in sparc backend.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262261
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Index: lib/Target/Sparc/SparcInstrInfo.td
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===================================================================
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--- lib/Target/Sparc/SparcInstrInfo.td
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+++ lib/Target/Sparc/SparcInstrInfo.td
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@@ -975,6 +975,33 @@ let rs1 = 0 in
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def : Pat<(ctpop i32:$src),
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(POPCrr (SRLri $src, 0))>;
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+// Atomic swap.
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+let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
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+ def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
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+
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+let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
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+ def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
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+ "membar $simm13", []>;
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+
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+let Constraints = "$val = $rd" in {
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+ def SWAPrr : F3_1<3, 0b001111,
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+ (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
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+ "swap [$addr], $rd",
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+ [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
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+ def SWAPri : F3_2<3, 0b001111,
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+ (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
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+ "swap [$addr], $rd",
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+ [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
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+}
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+
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+let Predicates = [HasV9], Constraints = "$swap = $rd" in
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+ def CASrr: F3_1<3, 0b111100,
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+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
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+ IntRegs:$swap),
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+ "cas [$rs1], $rs2, $rd",
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+ [(set i32:$rd,
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+ (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
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+
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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@@ -1036,4 +1063,17 @@ def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri
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def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
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def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
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+// store bar for all atomic_fence in V8.
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+let Predicates = [HasNoV9] in
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+ def : Pat<(atomic_fence imm, imm), (STBAR)>;
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+
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+// atomic_load_32 addr -> load addr
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+def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
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+def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
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+
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+// atomic_store_32 val, addr -> store val, addr
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+def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
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+def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
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+
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+
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include "SparcInstr64Bit.td"
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -1472,10 +1472,30 @@ SparcTargetLowering::SparcTargetLowering(TargetMac
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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}
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- // FIXME: There are instructions available for ATOMIC_FENCE
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- // on SparcV8 and later.
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- setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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+ // ATOMICs.
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+ // FIXME: We insert fences for each atomics and generate sub-optimal code
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+ // for PSO/TSO. Also, implement other atomicrmw operations.
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+ setInsertFencesForAtomic(true);
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+
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+ setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
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+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
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+ (Subtarget->isV9() ? Legal: Expand));
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+
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+
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+ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
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+
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+ // Custom Lower Atomic LOAD/STORE
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+ setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
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+ setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
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+
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+ if (Subtarget->is64Bit()) {
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+ setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
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+ setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
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+ setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
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+ setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
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+ }
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+
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if (!Subtarget->isV9()) {
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// SparcV8 does not have FNEGD and FABSD.
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setOperationAction(ISD::FNEG, MVT::f64, Custom);
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@@ -2723,6 +2743,16 @@ static SDValue LowerUMULO_SMULO(SDValue Op, Select
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return DAG.getMergeValues(Ops, 2, dl);
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}
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+static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
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+ // Monotonic load/stores are legal.
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+ if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
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+ return Op;
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+
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+ // Otherwise, expand with a fence.
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+ return SDValue();
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+}
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+
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+
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SDValue SparcTargetLowering::
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LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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@@ -2778,6 +2808,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) cons
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case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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case ISD::UMULO:
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case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
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+ case ISD::ATOMIC_LOAD:
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+ case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
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}
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}
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Index: lib/Target/Sparc/SparcInstr64Bit.td
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===================================================================
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--- lib/Target/Sparc/SparcInstr64Bit.td
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+++ lib/Target/Sparc/SparcInstr64Bit.td
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@@ -415,6 +415,32 @@ def SETHIXi : F2_1<0b100,
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"sethi $imm22, $rd",
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[(set i64:$rd, SETHIimm:$imm22)]>;
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}
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+
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+// ATOMICS.
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+let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
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+ def CASXrr: F3_1<3, 0b111110,
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+ (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
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+ I64Regs:$swap),
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+ "casx [$rs1], $rs2, $rd",
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+ [(set i64:$rd,
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+ (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
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+
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+} // Predicates = [Is64Bit], Constraints = ...
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+
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+let Predicates = [Is64Bit] in {
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+
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+def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
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+
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+// atomic_load_64 addr -> load addr
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+def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
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+def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
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+
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+// atomic_store_64 val, addr -> store val, addr
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+def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
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+def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
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+
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+} // Predicates = [Is64Bit]
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+
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// Global addresses, constant pool entries
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let Predicates = [Is64Bit] in {
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Index: test/CodeGen/SPARC/atomics.ll
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===================================================================
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--- test/CodeGen/SPARC/atomics.ll
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+++ test/CodeGen/SPARC/atomics.ll
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@@ -0,0 +1,63 @@
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+; RUN: llc < %s -march=sparcv9 | FileCheck %s
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+
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+; CHECK-LABEL: test_atomic_i32
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+; CHECK: ld [%o0]
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+; CHECK: membar
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+; CHECK: ld [%o1]
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+; CHECK: membar
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+; CHECK: membar
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+; CHECK: st {{.+}}, [%o2]
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+define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
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+entry:
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+ %0 = load atomic i32* %ptr1 acquire, align 8
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+ %1 = load atomic i32* %ptr2 acquire, align 8
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+ %2 = add i32 %0, %1
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+ store atomic i32 %2, i32* %ptr3 release, align 8
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+ ret i32 %2
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+}
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+
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+; CHECK-LABEL: test_atomic_i64
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+; CHECK: ldx [%o0]
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+; CHECK: membar
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+; CHECK: ldx [%o1]
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+; CHECK: membar
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+; CHECK: membar
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+; CHECK: stx {{.+}}, [%o2]
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+define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
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+entry:
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+ %0 = load atomic i64* %ptr1 acquire, align 8
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+ %1 = load atomic i64* %ptr2 acquire, align 8
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+ %2 = add i64 %0, %1
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+ store atomic i64 %2, i64* %ptr3 release, align 8
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+ ret i64 %2
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+}
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+
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+; CHECK-LABEL: test_cmpxchg_i32
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+; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
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+; CHECK: cas [%o1], %o0, [[R]]
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+
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+define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
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+entry:
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+ %b = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic
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+ ret i32 %b
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+}
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+
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+; CHECK-LABEL: test_cmpxchg_i64
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+; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
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+; CHECK: casx [%o1], %o0, [[R]]
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+
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+define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
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+entry:
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+ %b = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic
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+ ret i64 %b
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+}
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+
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+; CHECK-LABEL: test_swap_i32
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+; CHECK: or %g0, 42, [[R:%[gilo][0-7]]]
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+; CHECK: swap [%o1], [[R]]
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+
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+define i32 @test_swap_i32(i32 %a, i32* %ptr) {
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+entry:
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+ %b = atomicrmw xchg i32* %ptr, i32 42 monotonic
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+ ret i32 %b
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+}
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