de365b338d
Import from vendor-sys/alpine-hal/2.7 SVN rev.: 285432 HAL version: 2.7 Obtained from: Semihalf Sponsored by: Annapurna Labs
189 lines
5.4 KiB
C
189 lines
5.4 KiB
C
/*-
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_common HAL Common Layer
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* @{
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* @file al_hal_reg_utils.h
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*
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* @brief Register utilities used by HALs and platform layer
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*
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*
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*/
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#ifndef __AL_HAL_REG_UTILS_H__
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#define __AL_HAL_REG_UTILS_H__
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#include "al_hal_plat_types.h"
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#include "al_hal_plat_services.h"
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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#define AL_BIT(b) (1UL << (b))
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#define AL_ADDR_LOW(x) ((uint32_t)((al_phys_addr_t)(x)))
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#define AL_ADDR_HIGH(x) ((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16))
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/** get field out of 32 bit register */
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#define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift))
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/** set field of 32 bit register */
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#define AL_REG_FIELD_SET(reg, mask, shift, val) \
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(reg) = \
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(((reg) & (~(mask))) | \
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((((unsigned)(val)) << (shift)) & (mask)))
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/** set field of 64 bit register */
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#define AL_REG_FIELD_SET_64(reg, mask, shift, val) \
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((reg) = \
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(((reg) & (~(mask))) | \
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((((uint64_t)(val)) << (shift)) & (mask))))
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/** get single bit out of 32 bit register */
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#define AL_REG_BIT_GET(reg, shift) \
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AL_REG_FIELD_GET(reg, AL_BIT(shift), shift)
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#define AL_REG_BITS_FIELD(shift, val) \
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(((unsigned)(val)) << (shift))
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/** set single bit field of 32 bit register to a given value */
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#define AL_REG_BIT_VAL_SET(reg, shift, val) \
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AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
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/** set single bit of 32 bit register to 1 */
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#define AL_REG_BIT_SET(reg, shift) \
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AL_REG_BIT_VAL_SET(reg, shift, 1)
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/** clear single bit of 32 bit register */
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#define AL_REG_BIT_CLEAR(reg, shift) \
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AL_REG_BIT_VAL_SET(reg, shift, 0)
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#define AL_BIT_MASK(n) \
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(AL_BIT(n) - 1)
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#define AL_FIELD_MASK(msb, lsb) \
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(AL_BIT(msb) + AL_BIT_MASK(msb) - AL_BIT_MASK(lsb))
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/** clear bits specified by clear_mask */
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#define AL_REG_MASK_CLEAR(reg, clear_mask) \
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((reg) = (((reg) & (~(clear_mask)))))
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/** set bits specified by clear_mask */
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#define AL_REG_MASK_SET(reg, clear_mask) \
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((reg) = (((reg) | (clear_mask))))
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/** clear bits specified by clear_mask, and set bits specified by set_mask */
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#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask) \
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(reg) = (((reg) & (~(clear_mask))) | (set_mask))
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#define AL_ALIGN_UP(val, size) \
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((size) * (((val) + (size) - 1) / (size)))
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/** take bits selected by mask from one data, the rest from background */
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#define AL_MASK_VAL(mask, data, background) \
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(((mask) & (data)) | ((~mask) & (background)))
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/**
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* 8 bits register masked write
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*
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* @param reg
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* register address
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* @param mask
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* bits not selected (1) by mask will be left unchanged
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* @param data
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* data to write. bits not selected by mask ignored.
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*/
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static inline void
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al_reg_write8_masked(uint8_t __iomem *reg, uint8_t mask, uint8_t data)
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{
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uint8_t temp;
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temp = al_reg_read8(reg);
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al_reg_write8(reg, AL_MASK_VAL(mask, data, temp));
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}
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/**
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* 16 bits register masked write
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*
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* @param reg
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* register address
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* @param mask
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* bits not selected (1) by mask will be left unchanged
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* @param data
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* data to write. bits not selected by mask ignored.
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*/
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static inline void
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al_reg_write16_masked(uint16_t __iomem *reg, uint16_t mask, uint16_t data)
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{
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uint16_t temp;
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temp = al_reg_read16(reg);
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al_reg_write16(reg, AL_MASK_VAL(mask, data, temp));
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}
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/**
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* 32 bits register masked write
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*
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* @param reg
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* register address
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* @param mask
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* bits not selected (1) by mask will be left unchanged
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* @param data
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* data to write. bits not selected by mask ignored.
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*/
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static inline void
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al_reg_write32_masked(uint32_t __iomem *reg, uint32_t mask, uint32_t data)
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{
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uint32_t temp;
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temp = al_reg_read32(reg);
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al_reg_write32(reg, AL_MASK_VAL(mask, data, temp));
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}
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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#endif
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/* *INDENT-ON* */
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/** @} end of Common group */
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#endif
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