1f5e341b46
Add a subroutine for updating satp, for use when updating the active pmap. No functional change intended. Reviewed by: jhb MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D18462
315 lines
6.6 KiB
ArmAsm
315 lines
6.6 KiB
ArmAsm
/*-
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* Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.inc"
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#include <sys/syscall.h>
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#include <machine/asm.h>
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#include <machine/param.h>
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#include <machine/trap.h>
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#include <machine/riscvreg.h>
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#include <machine/pte.h>
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.globl kernbase
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.set kernbase, KERNBASE
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/* Trap entries */
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.text
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/* Reset vector */
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.text
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.globl _start
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_start:
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/* Get the physical address kernel loaded to */
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la t0, virt_map
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ld t1, 0(t0)
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sub t1, t1, t0
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li t2, KERNBASE
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sub s9, t2, t1 /* s9 = physmem base */
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mv s10, a0 /* s10 = hart id */
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mv s11, a1 /* s11 = dtbp */
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/* Direct secondary cores to mpentry */
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bnez s10, mpentry
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/*
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* Page tables
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*/
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/* Add L1 entry for kernel */
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la s1, pagetable_l1
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la s2, pagetable_l2 /* Link to next level PN */
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srli s2, s2, PAGE_SHIFT
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li a5, KERNBASE
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srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
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andi a5, a5, 0x1ff /* & 0x1ff */
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li t4, PTE_V
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slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
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or t6, t4, t5
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/* Store L1 PTE entry to position */
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li a6, PTE_SIZE
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mulw a5, a5, a6
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add t0, s1, a5
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sd t6, (t0)
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/* Level 2 superpages (512 x 2MiB) */
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la s1, pagetable_l2
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srli t4, s9, 21 /* Div physmem base by 2 MiB */
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li t2, 512 /* Build 512 entries */
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add t3, t4, t2
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li t5, 0
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2:
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li t0, (PTE_KERN | PTE_X)
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slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */
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or t5, t0, t2
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sd t5, (s1) /* Store PTE entry to position */
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addi s1, s1, PTE_SIZE
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addi t4, t4, 1
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bltu t4, t3, 2b
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/* Create an L1 page for early devmap */
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la s1, pagetable_l1
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la s2, pagetable_l2_devmap /* Link to next level PN */
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srli s2, s2, PAGE_SHIFT
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li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE)
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srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
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andi a5, a5, 0x1ff /* & 0x1ff */
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li t4, PTE_V
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slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
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or t6, t4, t5
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/* Store single level1 PTE entry to position */
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li a6, PTE_SIZE
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mulw a5, a5, a6
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add t0, s1, a5
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sd t6, (t0)
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/* Create an L2 page superpage for DTB */
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la s1, pagetable_l2_devmap
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mv s2, s11
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srli s2, s2, PAGE_SHIFT
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li t0, (PTE_KERN)
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slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */
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or t0, t0, t2
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/* Store PTE entry to position */
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li a6, PTE_SIZE
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li a5, 510
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mulw a5, a5, a6
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add t1, s1, a5
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sd t0, (t1)
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/* Page tables END */
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/* Setup supervisor trap vector */
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la t0, va
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sub t0, t0, s9
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li t1, KERNBASE
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add t0, t0, t1
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csrw stvec, t0
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/* Set page tables base register */
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la s2, pagetable_l1
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srli s2, s2, PAGE_SHIFT
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li t0, SATP_MODE_SV39
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or s2, s2, t0
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sfence.vma
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csrw satp, s2
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.align 2
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va:
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/* Setup supervisor trap vector */
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la t0, cpu_exception_handler
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csrw stvec, t0
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/* Ensure sscratch is zero */
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li t0, 0
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csrw sscratch, t0
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/* Initialize stack pointer */
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la s3, initstack_end
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mv sp, s3
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addi sp, sp, -PCB_SIZE
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/* Clear BSS */
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la a0, _C_LABEL(__bss_start)
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la s1, _C_LABEL(_end)
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1:
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sd zero, 0(a0)
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addi a0, a0, 8
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bltu a0, s1, 1b
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/* Fill riscv_bootparams */
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addi sp, sp, -40
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la t0, pagetable_l1
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sd t0, 0(sp) /* kern_l1pt */
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sd s9, 8(sp) /* kern_phys */
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la t0, initstack_end
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sd t0, 16(sp) /* kern_stack */
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li t0, (VM_MAX_KERNEL_ADDRESS - 2 * L2_SIZE)
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sd t0, 24(sp) /* dtbp_virt */
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sd s11, 32(sp) /* dtbp_phys */
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mv a0, sp
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call _C_LABEL(initriscv) /* Off we go */
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call _C_LABEL(mi_startup)
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.align 4
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initstack:
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.space (PAGE_SIZE * KSTACK_PAGES)
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initstack_end:
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ENTRY(sigcode)
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mv a0, sp
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addi a0, a0, SF_UC
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1:
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li t0, SYS_sigreturn
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ecall
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/* sigreturn failed, exit */
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li t0, SYS_exit
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ecall
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j 1b
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END(sigcode)
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/* This may be copied to the stack, keep it 16-byte aligned */
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.align 3
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esigcode:
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.data
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.align 3
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.global szsigcode
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szsigcode:
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.quad esigcode - sigcode
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.align 12
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pagetable_l1:
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.space PAGE_SIZE
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pagetable_l2:
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.space PAGE_SIZE
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pagetable_l2_devmap:
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.space PAGE_SIZE
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.align 3
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virt_map:
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.quad virt_map
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/* Not in use, but required for linking. */
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.align 3
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.globl __global_pointer$
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__global_pointer$:
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.space 8
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.globl init_pt_va
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init_pt_va:
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.quad pagetable_l2 /* XXX: Keep page tables VA */
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#ifndef SMP
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ENTRY(mpentry)
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1:
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wfi
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j 1b
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END(mpentry)
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#else
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/*
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* mpentry(unsigned long)
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*
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* Called by a core when it is being brought online.
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*/
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ENTRY(mpentry)
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/*
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* Calculate the offset to __riscv_boot_ap
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* for the current core, cpuid is in a0.
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*/
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li t1, 4
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mulw t1, t1, a0
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/* Get the pointer */
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la t0, __riscv_boot_ap
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add t0, t0, t1
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1:
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/* Wait the kernel to be ready */
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lw t1, 0(t0)
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beqz t1, 1b
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/* Setup stack pointer */
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la t0, secondary_stacks
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li t1, (PAGE_SIZE * KSTACK_PAGES)
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mulw t1, t1, s10
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add t0, t0, t1
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sub t0, t0, s9
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li t1, KERNBASE
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add sp, t0, t1
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/* Setup supervisor trap vector */
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la t0, mpva
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sub t0, t0, s9
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li t1, KERNBASE
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add t0, t0, t1
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csrw stvec, t0
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/* Set page tables base register */
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la s2, pagetable_l1
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srli s2, s2, PAGE_SHIFT
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li t0, SATP_MODE_SV39
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or s2, s2, t0
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sfence.vma
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csrw satp, s2
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.align 2
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mpva:
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/* Setup supervisor trap vector */
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la t0, cpu_exception_handler
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csrw stvec, t0
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/* Ensure sscratch is zero */
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li t0, 0
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csrw sscratch, t0
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call init_secondary
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END(mpentry)
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#endif
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