b031fef0fe
o Revamp the PIC I/F to only abstract the PIC hardware. The resource handling has been moved to nexus, where it belongs. o Include EOI and MASK+EOI methods to the PIC I/F in support of INTR_FILTER. o With the allocation of interrupt resources and setup of interrupt handlers in the common platform code we can delay talking to the PIC hardware after enumeration of all devices. Introduce a call to powerpc_intr_enable() in configure_final() to achieve that and have powerpc_setup_intr() only program the PIC when !cold. o As a consequence of the above, remove all early_attach() glue from the OpenPIC and Heathrow PIC drivers and have them register themselves when they're found during enumeration. o Decouple the interrupt vector from the interrupt request line. Allocate vectors increasingly so that they can be used for the intrcnt index as well. Extend the Heathrow PIC driver to translate between IRQ and vector. The OpenPIC driver already has the support for vectors in hardware. Approved by: re (blanket)
76 lines
2.9 KiB
C
76 lines
2.9 KiB
C
/*-
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* Copyright 2003 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_POWERMAC_HROWPICVAR_H_
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#define _POWERPC_POWERMAC_HROWPICVAR_H_
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#define HROWPIC_IRQMAX 64
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#define HROWPIC_IRQ_REGNUM 32 /* irqs per register */
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#define HROWPIC_IRQ_SHIFT 5 /* high or low irq word */
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#define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */
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/*
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* Register offsets within bank. There are two identical banks,
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* separated by 16 bytes. Interrupts 0->31 are processed in the
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* second bank, and 32->63 in the first bank.
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*/
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#define HPIC_STATUS 0x00 /* active interrupt sources */
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#define HPIC_ENABLE 0x04 /* interrupt asserts ppc EXTINT */
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#define HPIC_CLEAR 0x08 /* clear int source */
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#define HPIC_TRIGGER 0x0c /* edge/level int trigger */
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#define HPIC_PRIMARY 1 /* primary register bank */
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#define HPIC_SECONDARY 0 /* secondary register bank */
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/*
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* Convert an interrupt into a prim/sec bank number
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*/
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#define HPIC_INT_TO_BANK(x) \
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(((x) >> HROWPIC_IRQ_SHIFT) ^ 1)
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/*
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* Convert an interrupt into the bit number within a bank register
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*/
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#define HPIC_INT_TO_REGBIT(x) \
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((x) & HROWPIC_IRQ_MASK)
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#define HPIC_1ST_OFFSET 0x10 /* offset to primary reg bank */
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struct hrowpic_softc {
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device_t sc_dev; /* macio device */
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struct resource *sc_rres; /* macio bus resource */
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bus_space_tag_t sc_bt; /* macio bus tag/handle */
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bus_space_handle_t sc_bh;
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int sc_rrid;
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uint32_t sc_softreg[2]; /* ENABLE reg copy */
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u_int sc_vector[HROWPIC_IRQMAX];
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};
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#endif /* _POWERPC_POWERMAC_HROWPICVAR_H_ */
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